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WISTRON JE50-SB_图文
Discrete/UMA /Muxless Schematics Document
AMD GPU Manhattan(Park/Madison M2) and Vancouver(Seymour/Whistler M2)
AMD LIANO CPU FS1
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Date:
Document Number
Cover Page
JE50_SB Friday, April 01, 2011
SYSTEM DC/DC
JE50-SB Block Diagram
JE50-SB Project code:91.4M701.001
RT8239 INPUTS
41 OUTPUTS
5V_S5(5.5A) 3D3V_S5(5A)
AMD Liano APU ( FS1 socket 45W ) 722-Pin uFCPGA722
GPP X4 port DP X6 Port
X8 PCI EXPRESS GRAPHIC(Muxless Lan8 ~Lan15) X16 PCI EXPRESS GRAPHIC(Diserete only Lan0 ~Lan15) DP2(PCI EXPRESS Lan0~Lan3) DP0 HDMI
SYSTEM DC/DC
RT8207 Madison/Park Whistler/Seymour ATI
83,84,85,86,87 51 5V_S5
1D5V_S3(15A)
512MB/1GB/2GB
88,89,90,91
0D75_S0(1.2A)
SYSTEM DC/DC
RT8238 INPUTS
46 OUTPUTS
1D1V_S5(1.4A)
4,5,6,7,8 DP1 UMI-Link 4X4 TRAVIS PS8612 9
EDP Panel 49 LCD
1.Park/Seymour (64Mx16b*4)=&512MB 2.Park/Seymour(128MX16b *4) =&1GB 3.Madison/Whistler(64Mx16b*8)=&1GB 4.Madison/Whistler(128Mx16b*8)=&2GB
RT8238 (Diserete only)
1D2V_S0(5.2A)
1D8V_VGA_S0
49 MIC In 58 INT.SPKR 58
Codec ALC271X
FCH HUDSON-M3
Integrated Display DAC
PCB STACKUP
LAN Giga LAN BCM57785 TXFM
USB 3.0 (4parts) USB 2.0 (10 parts or 14 port if USB 3.0 do not used) GPP X4 port USB 1.1 (2 parts) SATA (6 parts) INT RTC
3D3V_S0 2D5V_S0 (200mA)
MS/MS Pro/xD /MMC/SD
5V_S5 VGA_CORE
PCIE x 1,USB x 1
Mini Card WLAN Mini-Card
BQ24745 INPUTS OUTPUTS CHG_PWR
18V DCBATOUT 6.0A
Line Out 58
INT CLK GEN HW MONITOR ACPI 1.1
PCIE x 1,USB x 1
USB 3.0 x3,USB x 3
17,18,19,20,21,22 LPC BUS SATA
USB 3.0 x1
USB3.0 3 PORT 61
ISL6267 INPUTS
42,43 OUTPUTS
VCC_CORE_S0 KBC ENE KB3936 BIOS
27 MXIC MX25L1605 60
USB HDD SATA
LPC DEBUG CONN. 71
0~1.55V DCBATOUT
0~1.55V 4A
Mini USB Blue Tooth
Touch Pad 69
INT. KB 69
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Block Diagram
Size A3 Date:
Document Number
JE50_SB Friday, April 01, 2011
REQUIRED SYSTEM STRAPS
USE this pin to determine INT/EXT CLK
PCH GPO199 PULL HIGH
PCI_CLK1 Allow PCIE GEN2
CLK_PCI_LPC USE DEBUG STRAPS
CLKGEN ENABLED (Use Internal)
S5_PLUS Mode DISABLE
non_Fusion CLOCK mode
Force PCIE GEN1
S5_PLUS Mode ENABLE
IGNORE DEBUG STRAPS
Fusion CLOCK mode
DISABLE EC
CLKGEN DISABLED (Use External)
PCIE Routing
APU LANE0 LANE1 LANE2 LANE3 FCH LANE0 LANE1 LANE2 LANE3
Pair 0 1 2 3 4 5 6 7 8 9 10 11 12 13 WLAN NC WWAN BT
Device USB 2.0 EXT2(For SW Debug)
LAN WWAN LAN
3G SIM Card NC CCD NC Card Reader USB 3.0 port 1 USB 2.0 EXT2 USB 2.0 EXT3 NC
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Table of Content
Size A3 Date:
Document Number
JE50_SB Friday, April 01, 2011
APU1F PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15
PCI EXPRESS
AA8 AA9 Y7 Y8 W5 W6 W8 W9 V7 V8 U5 U6 U8 U9 T7 T8 R5 R6 R8 R9 P7 P8 N5 N6 N8 N9 M7 M8 L5 L6 L8 L9 AC5 AC6 AC8 AC9 AB7 AB8 AA5 AA6 AF8 AF7 AE6 AE5 AE9 AE8 AD8 AD7 K5
P_GFX_RXP0 P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15 P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3 P_ZVDDP
P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9 P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15 P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3 P_ZVSS
AA2 AA3 Y2 Y1 Y4 Y5 W2 W3 V2 V1 V4 V5 U2 U3 T2 T1 T4 T5 R2 R3 P2 P1 P4 P5 N2 N3 M2 M1 M4 M5 L2 L3 AD4 AD5 AC2 AC3 AB2 AB1 AB4 AB5 AF1 AF2 AF5 AF4 AE3 AE2 AD1 AD2 K4
GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3 GTXP4 GTXN4 GTXP5 GTXN5 GTXP6 GTXN6 GTXP7 GTXN7 GTXP8 GTXN8 GTXP9 GTXN9 GTXP10 GTXN10 GTXP11 GTXN11 GTXP12 GTXN12 GTXP13 GTXN13 GTXP14 GTXN14 GTXP15 GTXN15
1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1 DIS_PX1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C401 C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 C417 C418 C419 C420 C421 C422 C423 C424 C425 C426 C427 C428 C429 C430 C431 C432
SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 PCIE_TXP0 PCIE_TXN0 PCIE_TXP1 PCIE_TXN1 PCIE_TXP2 PCIE_TXN2 31 31 66 66 65 65
GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3
UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX
C433 C434 C435 C436 C437 C438 C439 C440
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
APU_HDMI_DATA2 51 APU_HDMI_DATA2# 51 APU_HDMI_DATA1 51 APU_HDMI_DATA1# 51 APU_HDMI_DATA0 51 APU_HDMI_DATA0# 51 APU_HDMI_CLK 51 APU_HDMI_CLK# 51
LAN WWAN WLAN
17 17 17 17 17 17 17 17
31 31 66 66 65 65
PCIE_RXP0 PCIE_RXN0 PCIE_RXP1 PCIE_RXN1 PCIE_RXP2 PCIE_RXN2
PCIE_TXP0_C PCIE_TXN0_C PCIE_TXP1_C PCIE_TXN1_C PCIE_TXP2_C PCIE_TXN2_C
C441 C442 C443 C444 C457 C460
1 1 1 1 1 1
2 2 2 2 2 2
SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
LAN WWAN WLAN
UMI_FCH_APU_RX0P UMI_FCH_APU_RX0N UMI_FCH_APU_RX1P UMI_FCH_APU_RX1N UMI_FCH_APU_RX2P UMI_FCH_APU_RX2N UMI_FCH_APU_RX3P UMI_FCH_APU_RX3N 1D2V_S0
UMI_TX0P_C UMI_TX0N_C UMI_TX1P_C UMI_TX1N_C UMI_TX2P_C UMI_TX2N_C UMI_TX3P_C UMI_TX3N_C P_ZVSS
C445 C446 C447 C448 C449 C450 C451 C452
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
UMI_APU_FCH_TX0P UMI_APU_FCH_TX0N UMI_APU_FCH_TX1P UMI_APU_FCH_TX1N UMI_APU_FCH_TX2P UMI_APU_FCH_TX2N UMI_APU_FCH_TX3P UMI_APU_FCH_TX3N
17 17 17 17 17 17 17 17 PEG_TXP[0..15] PEG_TXP[0..15] 83 PEG_TXN[0..15] 83
2 P_ZVDDP R402 196R2F-GP
PEG_TXN[0..15]
R401 196R2F-GP
PEG_RXP[0..15] PEG_RXN[0..15]
PEG_RXP[0..15] 83 PEG_RXN[0..15] 83
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
APU_PCIE(1/5)
Size A3 Date:
Document Number
JE50_SB Friday, April 01, 2011
APU1A 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_BS0 M_A_BS1 M_A_BS2 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 M_A_DIM0_CLK_DDR0 M_A_DIM0_CLK_DDR#0 M_A_DIM0_CLK_DDR1 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE0 14 M_A_DIM0_CKE1 14 M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14 M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14 14 14 M_A_RAS# M_A_CAS# M_A_W E# 14 14 M_A_RST# M_A_EVENT# M_VREF_DQ_APU 1D5V_S3 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS#0 M_A_DQS1 M_A_DQS#1 M_A_DQS2 M_A_DQS#2 M_A_DQS3 M_A_DQS#3 M_A_DQS4 M_A_DQS#4 M_A_DQS5 M_A_DQS#5 M_A_DQS6 M_A_DQS#6 M_A_DQS7 M_A_DQS#7
MEMORY CHANNEL A
MEMORY CHANNEL B
U20 R20 R21 P22 P21 N24 N23 N20 N21 M21 U23 M22 L24 AA25 L21 L20 U24 U21 L23 E14 J17 E21 F25 AD27 AC23 AD19 AC15 G14 H14 G18 H18 J21 H21 E27 E26 AE26 AD26 AB22 AA22 AB18 AA18 AA14 AA15 T21 T22 R23 R24 H28 H27 Y25 AA27 V22 AA26 V21 W24 W23 H25 T24 W20 W21
MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
E13 J13 H15 J15 H13 F13 F15 E15 H17 F17 E19 J19 G16 H16 H19 F19 H20 F21 J23 H23 G20 E20 G22 H22 G24 E25 G27 G26 F23 H24 E28 F27 AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25 Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21 AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17 AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_BS0 M_B_BS1 M_B_BS2 15 15 15 15 15 15 15 15 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 M_B_DQS0 M_B_DQS#0 M_B_DQS1 M_B_DQS#1 M_B_DQS2 M_B_DQS#2 M_B_DQS3 M_B_DQS#3 M_B_DQS4 M_B_DQS#4 M_B_DQS5 M_B_DQS#5 M_B_DQS6 M_B_DQS#6 M_B_DQS7 M_B_DQS#7
T27 P24 P25 N27 N26 M28 M27 M24 M25 L26 U26 L27 K27 W26 K25 K24 U27 T28 K28 D14 A18 A22 C25 AF25 AG22 AH18 AD14 C15 B15 E18 D18 E22 D22 B26 A26 AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14 R26 R27 P27 P28 J26 J27 W27 Y28 V25 Y27 V24 V27 V28 J25 T25
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 MB_BANK0 MB_BANK1 MB_BANK2 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CKE0 MB_CKE1 MB_ODT0 MB_ODT1 MB_CS#0 MB_CS#1 MB_RAS# MB_CAS# MB_WE# MB_RESET# MB_EVENT#
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
A14 B14 D16 E16 B13 C13 B16 A16 C17 B18 B20 A20 E17 B17 B19 C19 C21 B22 C23 A24 D20 B21 E23 B23 E24 B25 B27 D28 B24 D24 D26 C27 AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24 AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20 AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16 AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
MA_BANK0 MA_BANK1 MA_BANK2 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CKE0 MA_CKE1 MA_ODT0 MA_ODT1 MA_CS#0 MA_CS#1 MA_RAS# MA_CAS# MA_WE# MA_RESET# MA_EVENT# M_VREF M_ZVDDIO
15 15 15 15
M_B_DIM0_CLK_DDR0 M_B_DIM0_CLK_DDR#0 M_B_DIM0_CLK_DDR1 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE0 15 M_B_DIM0_CKE1 15 M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15 M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15 15 15 M_B_RAS# M_B_CAS# M_B_W E# 15 M_B_RST# 15 M_B_EVENT#
2 R501 39R2F-GP
SAINE SAINE
APU_VREF_DQ
DDR_VREF_S3
M_VREF_DQ_APU
1D5V_S3 RN501
C501 SCD1U10V2KX-5GP
C502 SC1KP50V2KX-1GP
SRN1KJ-7-GP
M_A_EVENT# M_B_EVENT#
LAYOUT: place them close to APU
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
APU_DDR(2/5)
Size A3 Date:
Document Number
JE50_SB Friday, April 01, 2011
Boot Voltage
Boot Voltage
APU_DP_AUXP_CPU APU_DP_AUXN_CPU
RN609 2 1 SRN1K8J-GP
1.1 1.0 0.9 0.8
1.1 1.2 1.1 0.9
94 APU_DP_TXP0_CPU 94 APU_DP_TXN0_CPU APU_DP_AUXP_CPU APU_DP_AUXN_CPU APU_DP_AUXP_CPU APU_DP_AUXN_CPU 94 94
DP_AUX1P DP_AUX1N
4 3 SRN1K8J-GP
ANALOG/DISPLAY/MISC
3 OF 6 APU_TEST25_H_BYPASSCLK_H DP0_AUXP DP0_AUXN DP1_AUXP DP1_AUXN DP2_AUXP DP2_AUXN
DISPLAY PORT 0
9 LVDS_L0P_TRAVIS 9 LVDS_L0N_TRAVIS
UMA_PX UMA_PX
C602 2 C606 2
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
F2 F1 E3 E2 D2 D1 C2 C3
DP0_TXP0 DP0_TXN0 DP0_TXP1 DP0_TXN1 DP0_TXP2 DP0_TXN2 DP0_TXP3 DP0_TXN3 DP1_TXP0 DP1_TXN0 DP1_TXP1 DP1_TXN1 DP1_TXP2 DP1_TXN2
DISPLAY PORT 1
D4 D5 E5 E6 J5 J6 H4 H5 G5 G6 F4 F5 D7 E7 J7 H7 G7 F7 C6 C5 C7 D8 DP0_HPD DP1_HPD DP_AUX1P DP_AUX1N
C603 1 C601 1 C626 1 C627 1
2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP
UMA_PX_LVDS UMA_PX_LVDS UMA_PX UMA_PX
LVDS_CHP_TRAVIS LVDS_CHN_TRAVIS DP1_AUXP_R 19 DP1_AUXN_R 19
M_TEST APU_TEST9_ANALOGIN
2 R611 1 510R2J-1-GP 1 39R2F-GP 1 R602 2 0R2J-2-GP RN603
TRAVIS LVDS Panel
APU_TEST12_SCANSHIFTEND APU_TEST22_SCANSHIFTEN APU_TEST19_PLLTEST0 8 7 6 5
PCH_HDMI_CLK_R 51 PCH_HDMI_DATA_R 51 1D5V_S0
DP3_AUXP DP3_AUXN
DISPLAY PORT MISC.
1 2 3 4 SRN1KJ-4-GP
DP1_TX0P_R DP1_TX0N_R DP1_TX1P_R DP1_TX1N_R DP1_TX2P_R DP1_TX2N_R DP1_TX3P_R DP1_TX3N_R
UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX UMA_PX
1 1 1 1 1 1 1 1
C618 2 C619 2 C620 2 C621 2 C622 2 C623 2 C624 2 C625 2
SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
DP1_TX0P DP1_TX0N DP1_TX1P DP1_TX1N DP1_TX2P DP1_TX2N DP1_TX3P DP1_TX3N
K2 K1 J3 J2 H2 H1 G2 G3 AH7 AH6 AH4 AH3 B8 A8
DP4_AUXP DP4_AUXN DP5_AUXP DP5_AUXN DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD DP_BLON DP_DIGON DP_VARY_BL DP_AUX_ZVSS
3D3V_S0 R674 1 100KR2J-1-GP 2 R675 1 100KR2J-1-GP 2
RN602 APU_TEST18_PLLTEST1 APU_TEST21_SCANEN APU_TEST20_SCANCLK2 APU_TEST24_SCANCLK1 8 7 6 5 1 2 3 4 SRN1KJ-4-GP 1D2V_S0
VGA output from FCH
19 19 19 19 19 19
R653 100KR2J-1-GP
DP2_HPD 51 DP0_HPD
LVDS_CHN_TRAVIS
DP1_TXP3 DP1_TXN3 CLKIN_H CLKIN_L DISP_CLKIN_H DISP_CLKIN_L SVC SVD SIC SID RESET# PWROK PROCHOT# THERMTRIP# ALERT# TDI TDO TCK TMS TRST# DBRDY DBREQ# RSVD#E8 RSVD#K21 RSVD#AC11 VSS_SENSE VDDP_SENSE VDDNB_SENSE VDDIO_SENSE VDD_SENSE VDDR_SENSE SAINE
LVDS_CHP_TRAVIS
100MHz 100MHz
17 17 17 17 42 42
APU_CLKP APU_CLKN DISP_CLKP DISP_CLKN APU_SVC_R APU_SVD_R SCLK3 SDATA3 1 2
APU_BLEN APU_DIGON APU_BLPWM DP_AUX_ZVSS 1 R623 2 150R2F-1-GP 1D5V_S3 2
APU_TEST25_L_BYPASSCLK_L
1 R613 2 510R2J-1-GP 1 R643 2 1KR2J-1-GP
ALLOW_STOP
71 APU_RST_L_BUF 17 APU_RST# 17,36,71,97
H_CPUPWRGD_E
18 DY 18 1 R631 2 0R2J-2-GP
4 3 0R0402-PAD 1 R629 2 1 R630 2 0R0402-PAD 0R0402-PAD 2
APU_SIC APU_SID APU_RST#_R APU_PWRGD_R
AH11 AG11 AF10 AE10
SRN0J-6-GP 1 R632
110218 SB change to short pad
27 H_PROCHOT#
17 APU_PROCHOT# 1D5V_S3
AD10 APU_THERMTRIP#_VDDIO AG12 APU_ALERT# AH12 APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# C12 A12 A11 D12 B12 B11 C11 E8 K21 AC11
R636 K2R2J-2-GP 2
71 APU_TDI 71 APU_TDO 71 APU_TCK 71 APU_TMS 71 APU_TRST# 71 APU_DBRDY 71 APU_DBREQ#
APU_ALERT#_Q
42 APU_VDDNB_RUN_FB_L 1 R648 1 R649 0R0402-PAD 2 0R0402-PAD 2 TP620 42 APU_VDDNB_RUN_FB_H TP622 42 APU_VDD_RUN_FB_H TP623 PCH_TEMP_ALERT# 19,27 1 1 1 APU_RUN_FB_L APU_VDDP_FB_H APU_VDDIO_SUS_FB_H APU_VDDR_FB_H
R673 10KR2J-3-GP
42 APU_VDD_RUN_FB_L
84.0ND = 84.03904.P11
APU_ALERT# 2
2 3 Q603 PMBS3904-1-GP
B9 C8 A9 B10 C9 A10
TEST6 TEST9 TEST10 TEST12 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST21 TEST22 TEST23 TEST24 TEST25_H TEST25_L TEST28_H TEST28_L TEST30_H TEST30_L TEST31 TEST32_H TEST32_L TEST35 FS1R1 DMAACTIVE# THERMDA THERMDC
AA10 G10 APU_TEST9_ANALOGIN H10 H12 APU_TEST12_SCANSHIFTEND D9 APU_TEST14_BP0 APU_TEST15_BP1 E9 G9 APU_TEST16_BP2 H9 APU_TEST17_BP3 H11 APU_TEST18_PLLTEST1 G11 APU_TEST19_PLLTEST0 F12 APU_TEST20_SCANCLK2 E11 APU_TEST21_SCANEN D11 APU_TEST22_SCANSHIFTEN F10 G12 APU_TEST24_SCANCLK1 AH10 APU_TEST25_H_BYPASSCLK_H AH9 APU_TEST25_L_BYPASSCLK_L K7 K8 AA12 ANATSTIN_H AB12 ANATSTIN_L K22 M_TEST AB11 ANATSTOUT_H AA11 ANATSTOUT_L D10 TEST35 Y11 AB10 AE12 AD12
TP611 TP610 TP612 TP613 APU_TEST18_PLLTEST1 71 APU_TEST19_PLLTEST0 71
R612 300R2J-4-GP FS1R1 R617 300R2J-4-GP R615 1 10KR2J-3-GP 2
3D3V_AUX_S5
[AMD FAE Frank]: this is electrical key do not allow power to turn on if this pin is still &L&
FS1 package is open pin
in the furtur,FS1r2 will have this pin tied to VSS
if the wrong processor is plugged the socket
[AMD HDMI desing guidance]
TP601 TP617 TP618 TP619 FS1R1 36 ALLOW_STOP 17
This is more of a problem on desktop platforms (changing CPUs)
Strap define PU :Enable HDMI PD:Disable HDMI
19 1D5V_S3 DP_HPD1_R 1 R639 2 DP_HPD1_C_B 150KR2J-L1-GP 1
3 Q604 PMBS3904-1-GP 2 DP1_HPD
84.0ND = 84.03904.P11
R644 100KR2J-1-GP 1 R640 10KR2J-3-GP 2
APU_BLPWM_Q1
R658 4K7R2J-2-GP
1 R666 2 300R2J-4-GP 1 R665 2 300R2J-4-GP
H_CPUPWRGD_E
3 Q608 PMBS3904-1-GP APU_BLPWM_TRAVIS R622 1 0R2J-2-GP 2 9,27
H_CPUPWRGD_E
R670 10KR2J-3-GP 2
UMA_PX_EDP
R664 2K2R2J-2-GP
R656 2K2R2J-2-GP
APU_PROCHOT#_B
1 R637 2 300R2J-4-GP
R654 1 300R2J-4-GP 2
APU_RST# APU_RST#
APU_DIGON_Q
R663 4K7R2J-2-GP
R655 4K7R2J-2-GP
84.0ND = 84.03904.P11
UMA_PX_EDP
L_BKLT_CTRL_R
3D3V_VGA_S0
APU_PROCHOT#_VDDIO
H_CPUPWRGD_B
APU_PROCHOT#
RN607 3 4 2 1 SRN1K8J-GP APU_SVC_R APU_SVD_R
84.0ND = 84.03904.P11
H_CPUPWRGD_E 2
R651 1 0R2J-2-GP 2
9,49 DP_HPD0_C
R687 1 0R2J-2-GP 2
3 HPD_C 1 R641 2 HPD_C_B 150KR2J-L1-GP 1 2
SRN1K8J-GP
3 2 Q612 PMBS3904-1-GP
R662 100KR2J-1-GP
UMA_PX_EDP
EDP_HPD_PWR
UMA_PX_EDP
R669 10KR2J-3-GP
R667 10KR2J-3-GP
84.0ND = 84.03904.P11
APU_DIGON 2
UMA_PX_EDP
LVDS_VDD_EN_R 9,10
84.0ND = 84.03904.P11
3 Q610 PMBS3904-1-GP
R695 0R2J-2-GP
2 R694 0R2J-2-GP
84.0ND = 84.03904.P11
Q605 PMBS3904-1-GP EDP_HPD R690 1 0R2J-2-GP 2
2 1D5V_S3 H_CPUPWRGD 42 2 3 Q611 PMBS3904-1-GP 0R0402-PAD 2
R668 10KR2J-3-GP
R646 100KR2J-1-GP
R689 1 0R2J-2-GP 2 DP0_HPD
EDP_HPD_DET
2 R660 2K2R2J-2-GP 3D3V_S0 3D3V_VGA_S0
1 R642 10KR2J-3-GP
1D5V_S3 RN601 5 6 7 8 4 3 2 1 SRN1KJ-4-GP 2 1D5V_S3 RN604
1D5V_S3 APU_SID APU_SIC APU_THERMTRIP#_VDDIO APU_ALERT# 1
UMA_PX_EDP
R635 10KR2J-3-GP
APU_BLEN_Q
R693 0R2J-2-GP
R659 4K7R2J-2-GP
APU_THERMTRIP#_VDDIO_Q
1 2 3 4 SRN1KJ-4-GP
APU_TRST# APU_TDI APU_TMS APU_TCK
84.0ND = 84.03904.P11
3D3V_S5 1 3D3V_S5 1 APU_BLEN 1 2
UMA_PX_EDP
9,49 DP_HPD0_C
R691 1 33R2J-2-GP 2
L_BKLT_EN_R 9,10 3D3V_S5
EDP_HPD_DET
3 Q609 PMBS3904-1-GP
R638 10KR2J-3-GP 2
1D5V_S3 1 R616 2 1KR2J-1-GP APU_PROCHOT#
84.0ND = 84.03904.P11
APU_THERMTRIP#_VDDIO 2
APU_DBREQ# 1 R634 2 300R2J-4-GP
1D5V_S3 Q606
R650 10KR2J-3-GP
UMA_PX_EDP
R661 100KR2J-1-GP
UMA_PX_EDP
1D5V_S3 BSS138-8-GP G
&Variant Name& R652 10KR2J-3-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 9,27,85 Size Custom
D 3 Q601 PMBS3904-1-GP H_THERMTRIP# 18,36,85 APU_SIC S
9,27,85 APU_SID S Q607
APU_Control&Debug(3/5)
Document Number Friday, April 01, 2011 Rev
0920-SA S3 Power
℃ ℃ ℃ ℃
CPU exceeds to 125
BSS138-8-GP
C704 SCD22U10V2KX-1GP
C703 SCD01U16V2KX-3GP
C702 SCD01U16V2KX-3GP
C701 SC180P50V2JN-1GP
C1 D3 D6 E1 F3 F6 F8 G1 H3 H6 H8 J1 K3 K6 L1 L11 L19 M3 M6 M10 M18 N1 N11 N19 P3 P6 P10 P18 R1 R11 R19 T3 J9 J10 J11 J12 J14 J16 K9 K10 G28 H26 J28 K20 K23 K26 L22 L25 L28 M20 M23 M26 N22 N25 N28 P20 P23 P26 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AE11 AF11
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDP_A VDDP_A VDDP_A VDDP_A VDDR VDDR VDDR VDDR VDDA VDDA
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDP_B VDDP_B VDDP_B VDDP_B VDDR VDDR VDDR VDDR
T6 T10 T18 U1 U11 U19 V3 V6 V10 V18 W1 W11 W13 W15 W17 W19 Y3 Y6 Y10 Y12 Y14 Y16 Y18 Y20 AA1 AB3 AB6 AC1 AD3 AD6 AE1 K11 K12 K13 K14 K16 K17 K18 L18 R22 R25 R28 T20 T23 T26 U22 U25 U28 V20 V23 V26 W22 W25 W28 Y24 Y26 AA28 A3 A4 B3 B4 A5 A6 B5 B6
36A for VDD(35W CPU) 45A for VDD(45W CPU)
C714 C713 C712 C711 SCD22U10V2KX-1GP C710 SCD01U16V2KX-3GP C709 SC180P50V2JN-1GP
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
VDD: 10nF X3 10UF X7 0.22UF X2 180pF Cap for EMI requirment
18A for VDDNB(35W CPU) 22A for VDDNB(45W CPU)
SC10U6D3V5KX-1GP 2 1
SC10U6D3V5KX-1GP 2 1
SC10U6D3V5KX-1GP 2 1
C719 SC10U6D3V5KX-1GP
C717 SCD22U10V2KX-1GP
C716 SC180P50V2JN-1GP
C715 SC180P50V2JN-1GP
C721 SCD22U10V2KX-1GP
C720 SC180P50V2JN-1GP
VDDNB: 10UF X4 0.22UF X2 180pF Cap for EMI requirment 4A for VDDIO(35W CPU) 4.6A for VDDIO(45W CPU) VDDIO: 10UF X2 0.22UF X6 4.7uFUF X4 180pF Cap for EMI requirment 3.5A for VDDP(35W/45W)
SC10U6D3V5KX-1GP 2
C736 SCD22U10V2KX-1GP
C735 SCD22U10V2KX-1GP
C734 SCD22U10V2KX-1GP
C733 SC180P50V2JN-1GP
C732 SC4D7U6D3V3KX-GP
C731 SC4D7U6D3V3KX-GP
SC10U6D3V5KX-1GP 2
C729 SCD22U10V2KX-1GP
C728 SCD22U10V2KX-1GP
C727 SCD22U10V2KX-1GP SC4D7U6D3V3KX-GP
C726 SC180P50V2JN-1GP
C725 SC4D7U6D3V3KX-GP
C724 SC4D7U6D3V3KX-GP
C751 SC10U6D3V5KX-1GP
C750 SC10U6D3V5KX-1GP
C748 SCD22U10V2KX-1GP
C747 SCD22U10V2KX-1GP
C745 SC180P50V2JN-1GP
1D2V_S0 2D5V_S0
VDDP: 10UF X2 0.22uF X2 180pF Cap for EMI requirment 3A for VDDR(35W) 3.5A for VDDR(45W)
0.75A for VDDA(35W/45W)
C740 C739 SCD22U10V2KX-1GP C738 SCKX-1GP
1 1 1 1 1 1
C767 SCD22U10V2KX-1GP C766 SCD22U10V2KX-1GP C759 SC4D7U6D3V3KX-GP C758 SC4D7U6D3V3KX-GP C762 SC180P50V2JN-1GP C761 SC180P50V2JN-1GP C760 SC180P50V2JN-1GP
C744 SCD22U10V2KX-1GP SCD22U10V2KX-1GP
C743 SCD22U10V2KX-1GP SCD22U10V2KX-1GP
C742 SC180P50V2JN-1GP SC180P50V2JN-1GP
C741 SC180P50V2JN-1GP SC180P50V2JN-1GP
Decoupling between processor and DIMMs across VDDIO and VSS Split
VDDR: 4.7UF X2 0.22uF X2 180pF Cap for EMI requirment
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
APU_Power(4/5)
Size A3 Date:
Document Number
JE50_SB Friday, April 01, 2011
A7 A13 A15 A17 A19 A21 A23 A25 B7 C4 C10 C14 C16 C18 C20 C22 C24 C26 C28 D13 D15 D17 D19 D21 D23 D25 D27 E4 E10 E12 F9 F11 F14 F16 F18 F20 F22 F24 F26 F28 G4 G8 G13 G15 G17 G19 G21 G23 G25 J4 J8 J18 J20 J22 J24 K19 L4 L7 L10 M9 M11 M19 N4 N7 N10 N18 P9 P11 P19 R4 R7 R10 R18 T9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
T11 T19 U4 U7 U10 U18 V9 V11 V19 W4 W7 W10 W12 W14 W16 W18 Y9 Y22 AA4 AA7 AB9 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AB27 AC4 AC7 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC26 AC28 AD9 AD11 AE4 AE7 AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE27 AF3 AF6 AF9 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AH5 AH8 AH13 AH15 AH17 AH19 AH21 AH23 AH25
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
APU_VSS(5/5)
Size A3 Date:
Document Number
JE50_SB Friday, April 01, 2011
27 PS8612_RST#
R922 1 0R2J-2-GP 2
UMA_PX_LVDS
1 R908 2 10KR2J-3-GP PS8615_RST# LVDSA_DATA0# 49,94 LVDSA_DATA0 49,94 LVDSA_DATA1# 49,94 LVDSA_DATA1 49,94 LVDSA_DATA2# 49,94 LVDSA_DATA2 49,94 LVDSA_CLK# 49,94 LVDSA_CLK 49,94 PS8615_VDDIO
PS8615_VDDIO
110216 SB Bom change By edwin
UMA_PX_LVDS
C943 SC2D2U6D3V2MX-GP
PWMI: 0~100KHz, 0~100% duty cycle UMA_PX_LVDS
R918 6,27 APU_BLPWM_TRAVIS 1 2 APU_BLPWM_TRAVIS_R 0R2J-2-GP
Single Link LVDS
PS8615_VDDIO
UMA_PX_LVDS
L902 1 1 1 2 GBK1Y-GP
PS8615_VDDRX 1
UMA_PX_LVDS
GND NC#48 NC#47 TA0N TA0P TB0N TB0P VDDIO TC0N TC0P TCK0N TCK0P PWMI
C932 SC1U6D3V2KX-GP
68.nd = 68.
C942 SC1U6D3V2KX-GP
C938 SCD01U16V2KX-3GP
C937 SCD1U10V2KX-5GP
49 48 47 46 45 44 43 42 41 40 39 38 37
C939 SCD1U10V2KX-5GP 2
UMA_PX_LVDS
PS8615_VDDIO
UMA_PX_LVDS
UMA_PX_LVDS
L906 1 2 GBK1Y-GP
6 LVDS_L0P_TRAVIS 6 LVDS_L0N_TRAVIS PS8615_RST# PS8615_PD# 6,49 DP_HPD0_C PS8615_VDDIOX PS8615_I2C_CFG
PS8615_VDDIOX
6 LVDS_CHN_TRAVIS 6 LVDS_CHP_TRAVIS
C933 SC1U6D3V2KX-GP
68.nd = 68.
C944 SC4D7U6D3V3KX-GP
1 C946 SCD1U10V2KX-5GP 2
UMA_PX_LVDS
SW_OUT GNDX VDD12 TESTMODE GPIO0 RLV_CFG RLV_SSC CSDA/MSDA CSCL/MSCL REXT RLV_AMP GND
1 2 3 4 5 6 7 8 9 10 11 12
DAUXN DAUXP GND DRX0P DRX0N VDDRX RST# PD# HPD I2C_CFG VDDIOX VDDIOX
TD0N TD0P NC#34 NC#33 71.08612.A03 VDDIO NC#31 UMA_PX_LVDS ENPVCC/I2C_ADDR PWMO ENBLT VDD12 DDC_SDA DDC_SCL
36 35 34 33 32 31 30 29 28 27 26 25
UMA_PX_LVDS
C935 SCD1U10V2KX-5GP
LVDS_VDD_EN_R 6,10 L_BKLT_CTRL_R 6,10 L_BKLT_EN_R 6,10 2 2 2
LVDS_VDD_EN_R L_BKLT_CTRL_R L_BKLT_EN_R
0R2J-2-GP 1 R919 0R2J-2-GP 1 R920 0R2J-2-GP 1 R921
LVDS_VDD_EN 10,27,49,94 L_BKLT_CTRL 10,49,94 L_BKLT_EN 10,27,49,94 PS8615_VDD12
LVDS_DDC_DATA_R 94 LVDS_DDC_CLK_R 94
C947 SCD01U16V2KX-3GP
PH 4.7K 3D3V_S0_TRAVIS on page:94
UMA_PX_LVDS
PS8615_SW_OUT L905 1 2 IND-4D7UH-192-GP
PS8615_VDD12
PS8615_VDDRX
UMA_PX_LVDS
UMA_PX_LVDS
L904 1 2 GBK1Y-GP 1 1 C936 SC1U6D3V2KX-GP PS8615_VDDIO PS8615_SW_OUT 1
13 14 15 16 17 18 19 20 21 22 23 24
PS8612QFN48GTR-A0-GP
68.4R750.20C 68.nd = 68.4R71D.10E 2nd = 68. C934 UMA_PX_LVDS SC4D7U6D3V3KX-GP
UMA_PX_LVDS
R909 10KR2J-3-GP
R902: LVDS output swing control 4.99K for default swing, change the value for swing adjust UMA_PX_LVDS
PS8615_RLV_AMP PS8615_REXT CSCL/MSCL CSDA/MSDA PS8615_RLV_SSC PS8615_RLV_CFG PS8615_RLV_LNK 1 C940 SCD1U10V2KX-5GP 1 R906 1 R907 2 4K99R2F-L-GP 2 4K99R2F-L-GP
UMA_PX_LVDS
2 PS8615_VDD12
UMA_PX_LVDS Single Link LVDS
PS8615_PD# C941 SCD01U16V2KX-3GP 1
C945 SC1U6D3V2KX-GP 2
UMA_PX_LVDS
UMA_PX_LVDS
RN901 SRN4K7J-8-GP
UMA_PX_LVDS
1 2 Q901 1 2 3 6 5 4 SML1_CLK 6,27,85 CSCL/MSCL PS8615_I2C_CFG 2 R915 1 4K7R2J-2-GP
UMA_PX_LVDS
2 R910 1 4K7R2J-2-GP
UMA_PX_LVDS
default setting
PS8615_VDDIO
UMA_PX_LVDS
2N7002KDW-GP
I2C_CFG: Initial code loading selection, internal pull-down ~80K L: Hardware self configuration M: No initial code loading, external I2C control is expected L: Hardware self configuration H: Load initial code from external EEPROM through MSCL/MSDA DY PS8615_RLV_SSC 2 R916 1 4K7R2J-2-GP
2 R911 UMA_PX_LVDSPS8615_VDDIO 1 4K7R2J-2-GP
84.2N702.A3F 2nd = 84.DM601.03F
SML1_DATA 6,27,85
110221 SB Bom change By EMI
RLV_SSC: LVDS SSC selection, internal pull-down ~80K L: SSC off M: +/- 0.5% central spreading H: +/- 1% central spreading
PS8615_RLV_CFG 2 R917 1 4K7R2J-2-GP
L: SSC off
2 R912 1 4K7R2J-2-GP
UMA_PX_LVDS
PS8615_VDDIO
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K L: 8-bit LVDS, VESA mapping M: 8-bit LVDS, JEIDA mapping H: 6-bit LVDS, both VESA and JEIDA mapping
H: 6-bit LVDS, both VESA and JEIDA mapping
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Size A2 Date:
Document Number Friday, April 01, 2011
D1006 CH751H-40-1-GP K 3D3V_S0 U1005 LVDS_VDD_EN_A
RKR2F-GP 2
6,9 LVDS_VDD_EN_R
D1005 CH751H-40-1-GP K A C1008 SCD47U10V2KX-GP
NC#1 A GND
LVDS_VDD_EN_Y
RR2J-2-GP 1
LVDS_VDD_EN 9,27,49,94
NC7SV17P5X-GP
17,27,36,97 A_RST#
73.7SV17.00H UMA_PX
3D3V_S0 U CH751H-40-1-GP L_BKLT_EN_A K A
RKR2J-3-GP 2
RKR2F-L1-GP 2
NC#1 A GND
NC7SV17P5X-GP 6,9 L_BKLT_EN_R
C1009 SCD47U10V2KX-GP
73.7SV17.00H UMA_PX
84.2N702.J31 2ND = 84.2N702.031 UMA_PX
RR0402-PAD 2 RR0402-PAD 2
LVDS_SEQ_CTRL_R
LVDS_SEQ_CTRL
LVDS_CTRL_OE 3D3V_S0 U1003 LCD_CTRL_Q
6,9 L_BKLT_CTRL_R
RR2J-2-GP BKLT_CTRL_A 2
C1017 SCD1U50V3KX-GP
RR2J-2-GP 2
3D3V_S0 U1001
OE VCC A UMA_PX Y GND
RR2J-2-GP 1
LVDS_CTRL_B
74AHC1G126GW -GP
L_BKLT_CTRL 9,49,94
73.1G126.0AH
LCD_CTRL_OE NC7SZ08M5X-NL-GP RR2J-2-GP 2 L_BKLT_CTRL_Y
73.7SZ08.AAG
VDD_EN_U 3D3V_S0 UV_S0 D1004 CH751H-40-1-GP LCD_CTRL_R A K U1004 LCD_CTRL_U
L_BKLT_EN_R
D1003 CH751H-40-1-GP LCD_CTRL_D K A
RKR2J-1-GP 2
NC7SZ08M5X-NL-GP
RKR2J-1-GP 2
OE VCC A UMA_PX Y GND
74AHC1G126GW -GP
73.7SZ08.AAG
C1006 SCD47U10V2KX-GP
73.1G126.0AH
C1007 SCD47U10V2KX-GP
RR2J-2-GP 2
L_BKLT_EN 9,27,49,94
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Size A3 Date:
Document Number Friday, April 01, 2011
(Blanking)
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Date:
Document Number
JE50_SB Friday, April 01, 2011
(Blanking)
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Date:
Document Number
JE50_SB Friday, April 01, 2011
(Blanking)
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Date:
Document Number
JE50_SB Friday, April 01, 2011
ADM1 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 M_A_BS2 M_A_BS0 M_A_BS1 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 M_A_DIM0_ODT0 5 M_A_DIM0_ODT1 DDR_VREF_S3 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 DDR3-204P-125-GP NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 SA0_DIM0 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM0 SA1_DIM0 1 1 2 FC SCD1U10V2KX-5GP C1402 SC2D2U10V3KX-1GP SA1_DIM0
M_A_RAS# 5 M_A_WE# 5 M_A_CAS# 5 M_A_DIM0_CS#0 M_A_DIM0_CS#1 M_A_DIM0_CKE0 M_A_DIM0_CKE1 5 5 5 5
M_A_DIM0_CLK_DDR0 5 M_A_DIM0_CLK_DDR#0 5 M_A_DIM0_CLK_DDR1 5 M_A_DIM0_CLK_DDR#1 5 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 5 5 5 5 5 5 5 5
Intel HR DM tied to GND AMD still following previous design
PCH_SMBDATA 15,65,66 PCH_SMBCLK 15,65,66 M_A_EVENT# 5 3D3V_S0
SCD1U10V2KX-5GP
DY 110218 SB change to short pad
R 0R0402-PAD 0R0402-PAD 1 1
DDR_VREF_S3
C1412 can't stuff load too large let system abnormol at boot
STANDARD TYPE
SC1KP50V2KX-1GP
SCD1U10V2KX-5GP
C1411 SC1KP50V2KX-1GP
C1412 SC1U6D3V2KX-GP
PCH_SMBDATA PCH_SMBCLK PCH_SMBDATA PCH_SMBCLK
1 R04 C 1 1
0R2J-2-GP 0R2J-2-GP
SMB_DATA 18 SMB_CLK 18
DY 2 SC10P50V2JN-4GP DY 2 SC10P50V2JN-4GP
Place these caps close to VTT1 and VTT2.
C1419 SC1U6D3V2KX-GP
C1420 SC1U6D3V2KX-GP
C1421 SC1U6D3V2KX-GP
C1422 SC1U6D3V2KX-GP
C1418 SC10U6D3V5KX-1GP
FC1404 SCD1U10V2KX-5GP
SODIMM A DECOUPLING
C1403 SCD1U10V2KX-5GP SC10U6D3V5KX-1GP
C1404 SC10U6D3V5KX-1GP
C1405 SC10U10V5ZY-1GP
C1406 SC10U6D3V5KX-1GP
C1407 SC10U6D3V5KX-1GP
C1408 SC10U10V5ZY-1GP
C1409 SC10U6D3V5KX-1GP
C1410 SC10U6D3V5KX-1GP
M_A_RST# 1 C1425 SCD1U10V2KX-5GP
5 M_A_RST#
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Layout Note: Place these Caps near SO-DIMMA.
C1417 SCD1U10V2KX-5GP
Intel HR channel A & B RST tied toghter AMD have to separate channel A & B
62.1nd = 62.1rd = 62.10024.C21
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDR3-SODIMM1
Size A2 Date:
Document Number Friday, April 01, 2011
ADM2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 M_B_BS2 M_B_BS0 M_B_BS1 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 M_B_RST# 1 5 M_B_DIM0_ODT0 5 M_B_DIM0_ODT1 DDR_VREF_S3 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 1 2 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM1 SA1_DIM1 1 FC1501 SCD1U10V2KX-5GP C1501 2 SCD1U10V2KX-5GP M_B_RAS# 5 M_B_WE# 5 M_B_CAS# 5 M_B_DIM0_CS#0 M_B_DIM0_CS#1 M_B_DIM0_CKE0 M_B_DIM0_CKE1 5 5 5 5 3D3V_S0
M_B_DIM0_CLK_DDR0 5 M_B_DIM0_CLK_DDR#0 5 M_B_DIM0_CLK_DDR1 5 M_B_DIM0_CLK_DDR#1 5 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 5 5 5 5 5 5 5 5 SA0_DIM1 SA1_DIM1
0423 -Sabine David
1 RJ-3-GP R2-PAD 1 3D3V_S0
110218 SB change to short pad Intel HR DM tied to GND AMD still following previous design
PCH_SMBDATA 14,65,66 PCH_SMBCLK 14,65,66 M_B_EVENT# 5
Intel HR B channel address is 01 AMD B channel address is 10
C1502 SC2D2U10V3KX-1GP 2
C1516 can't stuff load too large let system abnormol at boot
DDR_VREF_S3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1515 SCD1U10V2KX-5GP
C1516 SC1U6D3V2KX-GP
SODIMM B DECOUPLING
1 1 1 1 1 1 1 1 C C C C 1 FC1502 SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U6D3V5KX-1GP 2
SC10U10V5ZY-1GP 2
SC10U10V5ZY-1GP 2
SC10U10V5ZY-1GP 2
Place these caps close to VTT1 and VTT2.
STANDARD TYPE
SCD1U10V2KX-5GP 2
SCD1U10V2KX-5GP 2
SCD1U10V2KX-5GP 2
C1518 SC1U6D3V2KX-GP
C1519 SC1U6D3V2KX-GP
C1520 SC1U6D3V2KX-GP
C1521 SC1U6D3V2KX-GP
C1522 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Layout Note: Place these Caps near SO-DIMMB.
C1514 SCD1U10V2KX-5GP
VREF_CA VREF_DQ RESET# VTT1 VTT2 DDR3-204P-123-GP
0423 -Sabine David 5
M_B_RST# 0D75V_S0
SO-DIMMB is placed farther from the Processor than SO-DIMMA
Intel HR channel A & B RST tied toghter AMD have to separate channel A & B
62.1nd = 62.1rd = 62.10017.X31
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDR3-SODIMM2
Size A2 Date:
Document Number Friday, April 01, 2011
(Blanking)
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Date:
Document Number
JE50_SB Friday, April 01, 2011
110307 SB change bom by siv
2 C1716 1 SC470P50V2KX-3GP RR2J-2-GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP 4 4 4 4 4 4 4 4 1D1V_S0 1 2 RF-3-GP UMI_APU_FCH_TX0P UMI_APU_FCH_TX0N UMI_APU_FCH_TX1P UMI_APU_FCH_TX1N UMI_APU_FCH_TX2P UMI_APU_FCH_TX2N UMI_APU_FCH_TX3P UMI_APU_FCH_TX3N 1 RR2F-GP APU_PCIE_CALRP APU_PCIE_CALRN PCIE_RST#_C A_RST#_R A_RX0P_C A_RX0N_C A_RX1P_C A_RX1N_C A_RX2P_C A_RX2N_C A_RX3P_C A_RX3N_C AE2 AD5 AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32 AB33 AB31 AB28 AB29 Y33 Y31 Y28 Y29 AF29 AF31 V33 V31 W30 W32 AB26 AB27 AA24 AA23 AA27 AA26 W27 V27 V26 W26 W24 W23 RKR2F-3-GP 2
Part 5 of 5
3D3V_S0 PCIE_RST# A_RST# UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N PCIE_CALRP PCIE_CALRN GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38 PCICLK4/14M_OSC/GPO39 PCIRST# AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42 GNT0# GNT1#/GPO44 GNT2#/SD_LED/GPO45 GNT3#/CLK_REQ7#/GPIO46 CLKRUN# LOCK#
PCI INTERFACE
10,27,36,97 A_RST# 4 4 4 4 4 4 4 4
UMI_FCH_APU_RX0P UMI_FCH_APU_RX0N UMI_FCH_APU_RX1P UMI_FCH_APU_RX1N UMI_FCH_APU_RX2P UMI_FCH_APU_RX2N UMI_FCH_APU_RX3P UMI_FCH_APU_RX3N
C08 1 C10 1 C12 1 C14 1
AF3 AF1 AF5 AG2 AF6 AB5 AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9 AF18 AE18 AC16 AD18
PCI_CLK1 PCI_CLK3_R PCI_CLK4_R R 1 1 22R2J-2-GP 2 0R0402-PAD 2 CLK_PCI_LPC 21,65,71 PCI_CLK4 21
1 PX4_SUPPORT RJ-3-GP 1 2 2
dGPU_PRSNT# RJ-3-GP
1 C1718 SCD1U16V2ZY-2GP
1 VRAM_800_900 dGPU_PRSNT# PX4_SUPPORT ZP_ODD_Support 1
-Sabin David for SW Jin define
3D3V_S0 3D3V_S0 2 2 RJ-3-GP RJ-3-GP
PCI EXPRESS INTERFACES
Debug Strap PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 21 21 21 21 PX R 0R2J-2-GP 2 1 ZP_ODD_Support RJ-3-GP 2
1 2 RJ-3-GP 1 VRAM_800_900
PCIE_RST#_C
RR2J-2-GP 2 1
F27 G30 G28 R26 T26 H33 H31 T24 T23 J30 K29 H27 H28 J27 K26 F33 F31 E33 E31 M23 M24 M27 M26 N25 N26 R23 R24 N27 R27 J26
PLT_RST# C1715 SC150P50V2KX-GP
DGPU_PWROK_1
Non Zero ODD
DGPU_PWROK 86,92,93
31,65,66,71,83
CLK_CALRN PCIE_RCLKP PCIE_RCLKN DISP_CLKP DISP_CLKN DISP2_CLKP DISP2_CLKN APU_CLKP APU_CLKN SLT_GFX_CLKP SLT_GFX_CLKN GPP_CLK0P GPP_CLK0N GPP_CLK1P GPP_CLK1N GPP_CLK2P GPP_CLK2N GPP_CLK3P GPP_CLK3N
CLOCK GENERATOR
3D3V_S0 2 2
6 6 DISP_CLKP DISP_CLKN R 1 1 0R0402-PAD 2 0R0402-PAD 2
EXT clock_Gen
FCHDISP_CLKP_R FCHDISP_CLKN_R
folloiwng Intel HR netname
For TRAVIS
6 6 APU_CLKP APU_CLKN R 1 1 R 0R0402-PAD 2 0R0402-PAD 2 2 2 0R2J-2-GP 0R2J-2-GP FCHAPU_CLKP_R FCHAPU_CLKN_R FCHGFX_CLKP_R FCHGFX_CLKN_R
R 10KR2J-3-GP 10KR2J-3-GP DY
TP1704 PE_GPIO0 PE_GPIO1 TP1705 PM_CLKRUN# 27 83 93
Muxless support PE_GPIO0 -&VGA_RESET PE_GPIO1 -&VGA_PowerEnable
83 CLK_PCIE_VGA 83 CLK_PCIE_VGA#
1 DIS_PX 1 DIS_PX
LDT_STP# connection is just for chipset automation purpose. It is an automatic test for AMD validation team only
1 1 0R0402-PAD 2 0R0402-PAD 2 2 2 0R2J-2-GP 0R2J-2-GP CLK_MINI1_R CLK_MINI1#_R CLK_SRC2 CLK_SRC2# LAN_CLK_R LAN_CLK#_R
PM_CLKRUN# checklist:No PU Res Integrated Resistor PU10K
SATA_ODD_DA# 56
WLAN 3G LAN
65 CLK_PCIE_WLAN 65 CLK_PCIE_WLAN# 66 CLK_PCIE_WWAN 66 CLK_PCIE_WWAN# 31 CLK_PCIE_LAN 31 CLK_PCIE_LAN#
3G 1 R R1741
INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35
0R0402-PAD 2 0R0402-PAD 2
GPP CLK port 0 1 2 3 4 5 6 7 8
Device New Card WLAN WWAN LAN X X X X X
CLKREQ# 0 1 2 3
GPP_CLK5P GPP_CLK5N GPP_CLK6P GPP_CLK6N GPP_CLK7P GPP_CLK7N
GPP_CLK4P GPP_CLK4N
LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/CLK_REQ6#/GPIO49 SERIRQ/GPIO48
B25 D25 D27 C28 A26 A29 A31 B27 AE27 AE19
LPCCLK0_R R1719 1 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
22R2J-2-GP 2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# INT_SERIRQ 27 27,65,71 27,65,71 27,65,71 27,65,71 27,65,71
LPC_CLK0 LPC_CLK1
INT_SERIRQ
110301 SB bom change
C1702 SC10P50V2JN-4GP 32K_X1
GPP_CLK8P GPP_CLK8N 14M_25M_48M_OSC
DMA_ACTIVE# PROCHOT# APU_PG LDT_STP# APU_RST# 32K_X1
G2 G4 H7 F1 F3 E6
32K_X1 32K_X2
G25 E28 E26 G26 F26
ALLOW_STOP 6 APU_PROCHOT# 6 H_CPUPWRGD_E 6,36,71,97 APU_RST# 6
32K_X2 S5_CORE_EN RTCCLK INTRUDER_ALERT# VDDBT_RTC_G
2 RR0402-PAD INTRUDER_ALERT#1 TP1701 RTC_AUX_S5
PCH_SUSCLK_KBC 27 RTC_CLK 21 32K_X2
110218 SB change to short pad
X1702 X-32D768KHZ-34GPU
82.ND = 82.30001.B21
C1706 SCD1U16V2ZY-2GP
25M_X1 RMR2J-1-GP 2
71.HUDM2.M03
G1701 GAP-OPEN
C1703 SC8P50V2CN-3GP C1720 SC1U6D3V2KX-GP
X 2 2 XTAL-25MHZ-102-GP
CL = 7pF Freq tolertance :+/- 20 ppm
&Variant Name&
C1704 SC12P50V2JN-3GP
82.ND = 82.RD = 82.30020.A31
C1705 SC12P50V2JN-3GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CL = 12pF Freq tolertance :+/- 30ppm
HUDSON-M2(1/6)
Size Custom Document Number Rev Date: Friday, April 01, 2011
3D3V_S5 RN1802
Device USB 2.0 EXT2(For SW Debug) WLAN NC WWAN BT 3G SIM Card USB PORT
SCLK1 SDATA1
Part 1 of 5
SRN10KJ-5-GP
110218 SB change to short pad
VGA_PD 27,29,36,44 PM_SLP_S3# 27,44 PM_SLP_S5# 27,97 PM_PWRBTN# 36 FCH_PWRGD
1 R1845 2 DY 10KR2J-3-GP
integrated PU DY
1 R33 2 10KR2J-3-GP 2 10KR2J-3-GP
EC_SCI# EC_SWI# PM_PWRBTN# PCIE_WAKE#
2 RKR2J-1-GP
PM_RSMRST#
2 RR0402-PAD
TP1801 TP1802 TP 2 0R0402-PAD 1 RR0402-PAD 1
PM_PWRBTN#_R FCH_TEST0 FCH_TEST1 FCH_TEST2 EC_A20M#_R EC_KB_RST#_R EC_SCI#
AB6 R2 W7 T3 W2 J4 N7 T9 T10 V9 AE22 AG19 R9 C26 T5 U4 K1 V7 R10 AF19 U2
PCIE_RST2#/PCI_PME#/GEVENT4# RI#/GEVENT22# SPI_CS3#/GBE_STAT1/GEVENT21# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD TEST0 TEST1/TMS TEST2 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/GEVENT23# LPC_PD#/GEVENT5# SYS_RESET#/GEVENT19# WAKE#/GEVENT8# IR_RX1/GEVENT20# THRMTRIP#/SMBALERT#/GEVENT2# WD_PWRGD RSMRST# CLK_REQ4#/SATA_IS0#/GPIO64 CLK_REQ3#/SATA_IS1#/GPIO63 SMARTVOLT1/SATA_IS2#/GPIO50 CLK_REQ0#/SATA_IS3#/GPIO60 SATA_IS4#/FANOUT3/GPIO55 SATA_IS5#/FANIN3/GPIO59 SPKR/GPIO66 SCL0/GPIO43 SDA0/GPIO47 SCL1/GPIO227 SDA1/GPIO228 CLK_REQ2#/FANIN4/GPIO62 CLK_REQ1#/FANOUT4/GPIO61 IR_LED#/LLB#/GPIO184 SMARTVOLT2/SHUTDOWN#/GPIO51 DDR3_RST#/GEVENT7#/VGA_PD GBE_LED0/GPIO183 SPI_HOLD#/GBE_LED1/GEVENT9# GBE_LED2/GEVENT10# GBE_STAT0/GEVENT11# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
USBCLK/14M_25M_48M_OSC
G8 B9 H1 H3 H6 H5 H10 G10 K10 J12 G12 F12 K12 K13 B11 D11 E10 F10 C10 A10 H9 G9 A8 C8 F8 E8 C6 A6 C5 A5 C1 C3 E1 E3 C16 USBSS_CALRP A16 USBSS_CALRN A14 C14 C12 A12 D15 B15 E14 F14 F15 G15 H13 G13 J16 H16 J15 K15 H19 G19 G22 G21 E22 H22 J22 H21 K21 K22 F22 F24 E24 B23 C24 F18
SCL2 SDAT2 SCLK3 SDATA3 R18 1 USB_PP1 65 USB_PN1 65 USB_PP0 82 USB_PN0 82 USB_PP7 49 USB_PN7 49 USB_PP6 82 USB_PN6 82 USB_PP5 66 USB_PN5 66 USB_PP4 63 USB_PN4 63 USB_PP3 66 USB_PN3 66 USB20_DP3 82 USB20_DM3 82 USB20_DP2 82 USB20_DM2 82 USB20_DP1 62 USB20_DM1 62 USB_RCOMP
2 RK8R2F-GP
4 5 6 7 8 9 10 11 12 13
USB_RCOMP USB_FSD1P/GPIO186 USB_FSD1N USB_FSD0P/GPIO185 USB_FSD0N USB_HSD13P USB_HSD13N USB_HSD12P USB_HSD12N USB_HSD11P USB_HSD11N USB_HSD10P USB_HSD10N USB_HSD9P USB_HSD9N USB_HSD8P USB_HSD8N USB_HSD7P USB_HSD7N USB_HSD6P USB_HSD6N
110218 SB change to short pad
27 27 27 H_A20GATE H_RCIN# EC_SCI#
CCD USB PORT USB 3.0 ccd 3.0 USB 3.0 on board port USB 3.0 ext port 1 USB 3.0 ext port 2
1 R1843 2 DY 10KR2J-3-GP 1 R1839 2DY 10KR2J-3-GP
31,65,66 PCIE_WAKE# 6,36,85 H_THERMTRIP# PM_RSMRST# RV_S0
PCIE_WAKE# FCH_THERMTRIP# WD_PWRGD
integrated PU (FCH Rev 1.2 updated)
1 R1844 2 DY 10KR2J-3-GP
0R2J-2-GP 2 1 RKR2J-3-GP
have not use OC function in JE40 Project
integrated PU is not supported when the pin if configured for USB OC (FCH Rev 1.2 updated)
C1802 SCD1U10V2KX-5GP
31 PCIE_CLK_LAN_REQ#
0R0402-PAD 1 R1829
PCIE_CLK_LAN_RQ1#_R FCH_GPIO55 HDA_SPKR_R
0R0402-PAD 14 14 SMB_CLK SMB_DATA 0R0402-PAD 0R0402-PAD
66 CLK_PCIE_WWAN_REQ# 65 CLK_PCIE_WLAN_REQ#
SCLK1 SDATA1 CLK_PCIE_WWAN_REQ#_R CLK_PCIE_WLAN_REQ#_R VGA_PD
base on AMD suggestion, make sure Travis_EN# function first so confrim function work nornally or not on GPIO66,if work nornally, BIOS can re-programming pin to GPIO55 (DYR1841,stuff R1842) and change Travis_EN# to GPIO55 in the furtur keep Gevent4# for PCIE_RST2 used AMD define two function pin on same pin in CRB
SMB_CLK SMB_DATA 29 HDA_CODEC_BITCLK 29 HDA_CODEC_SDOUT 29 HDA_SDIN0
integrated PU
H_A20GATE H_RCIN#
85 PEG_CLKREQ#
1 RR2J-2-GP
AG24 AE24 AE26 AF22 AH17 AG18 AF24 AD26 AD25 T7 R7 AG25 AG22 J2 AG26 V8 W8 Y6 V10 AA8 AF25 M7 R8 T1 P6 F5 P5 J7 T8
ACPI / WAKE UP EVENTS
USB_HSD5P USB_HSD5N USB_HSD4P USB_HSD4N USB_HSD3P USB_HSD3N USB_HSD2P USB_HSD2N USB_HSD1P USB_HSD1N USB_HSD0P USB_HSD0N USBSS_CALRP USBSS_CALRN USB_SS_TX3P USB_SS_TX3N USB_SS_RX3P USB_SS_RX3N USB_SS_TX2P USB_SS_TX2N
2 10KR2J-3-GP 2 10KR2J-3-GP
27 EC_SWI# 56 SATA_ODD_PRSNT# 56 ODD_DA_Q
1 RR2J-2-GP
USB_OC7# EC_SWI# SATA_ODD_PRSNT#_R
BLINK/USB_OC7#/GEVENT18# USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GEVENT17# USB_OC4#/IR_RX0/GEVENT16# USB_OC3#/AC_PRES/TDO/GEVENT15# USB_OC2#/TCK/GEVENT14# USB_OC1#/TDI/GEVENT13# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
2 1KR2F-3-GP 2 1KR2F-3-GP
USB30_TXDP3 82 USB30_TXDN3 82 USB30_RXDP3 82 USB30_RXDN3 82 USB30_TXDP2 82 USB30_TXDN2 82 USB30_RXDP2 82 USB30_RXDN2 82 USB30_TXDP1 35 USB30_TXDN1 35 USB30_RXDP1 35 USB30_RXDN1 35 USB30_TXDP0 49 USB30_TXDN0 49 USB30_RXDP0 49 USB30_RXDN0 49
SRN2K2J-1-GP
33R2J-2-GP 33R2J-2-GP
HDA_BITCLK HDA_SDOUT HDA_SDIN0
29 HDA_CODEC_SYNC 29 HDA_CODEC_RST#
1 EC1802 SC180P50V2JN-1GP 33R2J-2-GP 2 33R2J-2-GP 2
HDA_SYNC HDA_RST#
AB3 AB1 AA2 Y5 Y3 Y1 AD6 AE4 K19 J19 J21 D21 C20 D23 C22 F21 E20 F20 A22 E18 A20 J18 H18 G18 B21 K18 D19 A18 C18 B19 B17 A24 D17
USB 3.0 ext port 2
AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 AZ_SDIN3/GPIO170 AZ_SYNC AZ_RST#
USB 3.0 ext port 1
USB_SS_RX2P USB_SS_RX2N
EC1801 SC180P50V2JN-1GP
PS2_DAT/SDA4/GPIO187 PS2_CLK/CEC/SCL4/GPIO188 SPI_CS2#/GBE_STAT2/GPIO166 PS2KB_DAT/GPIO189 PS2KB_CLK/GPIO190 PS2M_DAT/GPIO191 PS2M_CLK/GPIO192 KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/XDB0/GPIO223 KSO_15/XDB1/GPIO224 KSO_16/XDB2/GPIO225 KSO_17/XDB3/GPIO226
USB_SS_TX1P USB_SS_TX1N USB_SS_RX1P USB_SS_RX1N USB_SS_TX0P USB_SS_TX0N USB_SS_RX0P USB_SS_RX0N
USB 3.0 on board port
Name H_A20GATE H_RCIN# EC_SCI# H_THERMTRIP# FCH_PCIE_RST# MEM_Hot# EC_SWI# PCIE_WAKE# USB_OC0# USB_OC1# USB_OC2# SATA_ODD_PRSNT# ODD_DA USB_OC5# EC_SWI# USB_OC7# EC_SMI# SATA_ODD_DA# INT_SERIRQ CLK_PCIE_NEW_REQ# CLK_PCIE_WLAN_REQ# CLK_PCIE_WWAN_REQ# PCIE_CLK_LAN_RQ1# PEG_CLKREQ#
Integrated Resistor 8.2K PU 8.2K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 10K PU 8.2K PU 8.2K PU
External Resistor 10K PU 3.3_S0 10K PU 3.3_S0 10K PU 3.3_S5 10K PU 3.3_S5 DY DY DY DY
HDA_SDIN0 HDA_CODEC_BITCLK HDA_CODEC_RST#
KBRST# PME# THRIPTRIP# PCIE_RST2# Gevent5 Gevent6 WAKE# USB_OC0# USB_OC1# USB_OC2# Gevent15# Gevent16# USB_OC5# Gevent17# USB_OC7# LPC_SMI# GPIO35 SERIRQ CLK_REQ0 CLK_REQ1 CLK_REQ2 CLK_REQ3 CLK_REQG
SCL2/GPIO193 SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196 EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM3/EC_TIMER3/GPIO200
EMBEDDED CTRL
RN1805 SCLK3 SDATA3 EC_PWM2 21 6 6 SCL2 SDAT2
SRN10KJ-5-GP
If not used SMBUS or GPIO ,PD 10K
SRN10KJ-6-GP
Checklist suggestion do not stuff by default
10K PU 3.3_S5 10K PU 3.3_S5
KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208
3D3V_S5 RN1806 SCLK3 SDATA3
SRN10KJ-5-GP
71.HUDM2.M03
3D3V_AUX_S5
10K PU 3.3_S0 10K PU 3.3_S5 10K PU 3.3_S0
2 RKR2J-1-GP
PM_RSMRST# 1 RKR2J-1-GP
RSMRST#_KBC 27 3V_5V_POK 41 &Variant Name&
8.2K PU 8.2K PU 8.2K PU 8.2K PU 8.2K PU 8.2K PU
51123_PGOOD_2
2N7002KDW-GP
84.2N702.A3F 2nd = 84.DM601.03F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
HUDSON-M2(2/6)
Size Custom Date: Document Number Rev Friday, April 01, 2011
Part 2 of 5
1st SATA HDD
56 56 56 56 56 56 56 56
SATA_TXP0 SATA_TXN0 SATA_RXN0 SATA_RXP0 SATA_TXP1 SATA_TXN1 SATA_RXN1 SATA_RXP1
AK19 AM19 AL20 AN20 AN22 AL22 AH20 AJ20 AJ22 AH22
SATA_TX0P SATA_TX0N SATA_RX0N SATA_RX0P SATA_TX1P SATA_TX1N SATA_RX1N SATA_RX1P SATA_TX2P SATA_TX2N SATA_RX2N SATA_RX2P SATA_TX3P SATA_TX3N SATA_RX3N SATA_RX3P SATA_TX4P SATA_TX4N SATA_RX4N SATA_RX4P SATA_TX5P SATA_TX5N
SERIAL ATA GBE LAN SD CARD
SD_CLK/SCLK_2/GPIO73 SD_CMD/SLOAD_2/GPIO74 SD_CD#/GPIO75 SD_WP/GPIO76 SD_DATA0/SDATI_2/GPIO77 SD_DATA1/SDATO_2/GPIO78 SD_DATA2/GPIO79 SD_DATA3/GPIO80 GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST# GBE_PHY_INTR SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1#/GPIO165 ROM_RST#/SPI_WP#/GPIO161 VGA_RED
AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14 AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9 V6 V5 V3 T6 V1 R L32 M29 M28 N30 M33 N32 K31 V28 V29 U28 T31 T33 T29 T28 R32 R30 P29 P28 C29 N2 M3 L2 N4 P1 P3 M1 M5 AG16 AH10 A28 G27 L4 PSW_CLR# GPIO176 AUD_HP GPIO178 GPIO179 GPIO180 VIN_VDDR GPIO182 3D3V_S5 AUXCAL DP1_TX0P_R DP1_TX0N_R DP1_TX1P_R DP1_TX1N_R DP1_TX2P_R DP1_TX2N_R DP1_TX3P_R DP1_TX3N_R 6 6 6 6 6 6 6 6 HUDSON_DAC_RESET R06 1 150R2F-1-GP 2 150R2F-1-GP 2 150R2F-1-GP 2 CRT_RED 94 CRT_GREEN 94 CRT_BLUE 94
GBE_COL GBE_CRS GBE_MDIO 1 RKR2J-3-GP 3D3V_S5
AM23 AK23 AH24 AJ24
RN1903 GBE_RXERR 8 7 6 5 1 2 3 4 SRN10KJ-6-GP
2nd SATA HDD
AN24 AL24 AL26 AN26 AJ26 AH26 AN29 AL28 AK27 AM27 AL29 AN31 AL31 AL33 AH33 AH31 AJ33 AJ31 RKR2F-3-GP 2 1 2 RF-1-GP 68 SATA_LED#
NC#AL29 NC#AN31 NC#AL31 NC#AL33 NC#AH33 NC#AH31 NC#AJ33 NC#AJ31
SATA_RX5N SATA_RX5P
UMA_PX UMA_PX UMA_PX
VGA_GREEN VGA_BLUE VGA_HSYNC/GPO68 VGA_VSYNC/GPO69
CRT_HSYNC 94 CRT_VSYNC 94 CRT_DDC_DATA 94 CRT_DDC_CLK 94 1 R1907 UMA_PX 2 715R2F-GP DP1_AUXP_R 6 DP1_AUXN_R 6 2 1 RF-L1-GP-U
SATA_CALP SATA_CALN
AF28 AF27 AD22 AF21
VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71 VGA_DAC_RSET AUX_VGA_CH_P AUX_VGA_CH_N AUXCAL
SATA_CALRP SATA_CALRN SATA_ACT#/GPIO67 SATA_X1
[checklist]: Integrated Clock Mode =& Left unconnected
AG21 SATA_X2
VGA MAINLINK
ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N ML_VGA_HPD/GPIO229
RKR2J-3-GP 2 DP_HPD1_R 6 3D3V_S5 1
3D3V_VDDAN_DAC_S0_R
56 SATA_ODD_PWRGT RKR2J-3-GP 2
AH16 AM15 AJ16 AK15 AN16 AL16
FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54 FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58
HW MONITOR
APU_TALERT# GPIO171 FCH_USB3.0PORT_EN# MB_THRMDA_FCH APU_TALERT# 1 RR2J-2-GP
6,27 PCH_TEMP_ALERT# RN 6 5 1 2 3 4 SRN10KJ-6-GP GPIO171 FCH_USB3.0PORT_EN# MB_THRMDA_FCH
K6 K5 K3 M6
VIN0/GPIO175 VIN1/GPIO176 VIN2/SDATI_1/GPIO177 VIN3/SDATO_1/GPIO178 VIN4/SLOAD_1/GPIO179 VIN5/SCLK_1/GPIO180 VIN6/GBE_STAT3/GPIO181 VIN7/GBE_LED3/GPIO182 NC#AG16 NC#AH10 NC#A28 NC#G27 NC#L4
1 RJ-3-GP 2 RJ-3-GP 2 29 1 RJ-3-GP 2 2 AUD_HP 1 RJ-3-GP
TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT#/GPIO174
DY 71.HUDM2.M03
RN 6 5 1 2 3 4 SRN10KJ-6-GP GPIO180 GPIO182 GPIO178 GPIO179
VDDIO 1.5V
MEM_1V5 H L
MEM_1V35 Don't Care H 512M 1G
Vram size1 (GPIO176) 0 1 1 0
Vram size2 (GPIO177) 0 1 0 1
2G undfine
&Variant Name&
PSW_CLR# 2 G1901 GAP-OPEN 1 RKR2J-3-GP 2 VIN_VDDR
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
0927-SA If not used HWM or GPIO ,PD 10K
HUDSON-M2(3/6)
Size Custom
Document Number
Date: Friday, April 01, 2011
Part 3 of 5
1D1V_S0 T14 T17 T20 U16 U18 V14 V17 V20 Y17 H26 J25 K24 L22 M22 N21 N22 P22
102mA AB17
C2002 SC10U6D3V5KX-1GP C2003 SCD1U10V2KX-5GP C2004 SCD1U10V2KX-5GP C2005 SCD1U10V2KX-5GP AB18 AE9 AD10 AG7 AC13 AB12 AB13 AB14 AB16 1 1 1 1
PCI/GPIO I/O
VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDPL_33_SYS VDDPL_33_DAC VDDPL_33_ML VDDAN_33_DAC VDDPL_33_SSUSB_S VDDPL_33_USB_S VDDPL_33_PCIE VDDPL_33_SATA LDO_CAP VDDPL_11_DAC VDDAN_11_ML VDDAN_11_ML VDDAN_11_ML VDDAN_11_ML VDDIO_33_GBE_S
VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDCR_11 VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA
1 1 1 C2006 SC1U6D3V2KX-GP C2007 SC1U6D3V2KX-GP C2009 SCD1U10V2KX-5GP 1 C2010 SCD1U10V2KX-5GP
VDDAN_11_CLK_B2 1 G
84.03400.B37
VDDAN_11_CLK D S Q2004 AO3400A-GP C2014 SC1U6D3V2KX-GP RR3J-0-U-GP 2 1D1V_S0
3D3V_VPPL_SYS_S0 3D3V_VDDPL_MLDAC_S0 3D3V_S0
220 ohm 300mA
VDDPL_3.3V_PCIE 1 C2016 SC2D2U10V3KX-1GP C2017 SCD1U10V2KX-5GP 1D1V_S0 L PBY0Y-N-GP
68.0nd = 68.
2 0R2J-2-GP
CLKGEN I/O
L BLM15AG221SS1D-GP
3D3V_VDDAN_DAC_S0_R 3D3V_VDDPL_SSUSB_S5 3D3V_VDDPL_USB_S5
50mA H24 20mA V22 12mA U22 30mA T22 11mA L18 14mA D7 11mAAH29 12mAAG28
VDDAN_11_CLK 1 1 1
1 2 C2065 SCD1U10V2KX-5GP
C2011 SC1U6D3V2KX-GP
C2012 SCD1U10V2KX-5GP
C2013 SCD1U10V2KX-5GP
AB24 1088mA Y21 AE25 AD24 AB23 AA22 AF26 AG27 AA21 1337mA Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19
SC4D7U6D3V3KX-GP VDDPL_11_DAC
220 ohm 300mA
VDDPL_3.3V_SATA 1 C2024 SC2D2U10V3KX-1GP C2025 SCD1U10V2KX-5GP
3D3V_S5 1 1 1 1 U SC1U6D3V2KX-GP 2 C2075 SC2D2U10V3KX-1GP 1 2 3 IN GND DY SHDN# G9141T11U-GP OUT SET 5 4 C2029 SC1U6D3V2KX-GP C2030 SCD1U10V2KX-5GP C2031 SCD1U10V2KX-5GP
2 10KR2F-2-GP
SERIAL ATA
68.0nd = 68.
SCD1U10V2KX-5GP
PCI EXPRESS
L BLM15AG221SS1D-GP
C2026 SC4D7U6D3V3KX-GP
7mA 226mA Y22
V23 V24 V25
C2019 SC1U6D3V2KX-GP
C2021 SCD1U10V2KX-5GP
C2022 SCD1U10V2KX-5GP
C2020 SC1U6D3V2KX-GP
C2023 SC10U6D3V5KX-1GP
C2028 SCD1U10V2KX-5GP
C2077 SC4D7U6D3V3KX-GP
VDDCR_11_GBE_S VDDCR_11_GBE_S
74.09141.03F
1 RR2F-L-GP
VDDIO_GBE_S VDDIO_GBE_S
220 ohm 3A
3D3V_USB_S5
Vout=1.0*(1+R1/R2)
68.ND = 68.
3.3V_S5 I/O
C2037 SC1U6D3V2KX-GP
C2038 SC1U6D3V2KX-GP
C2039 SC10U6D3V5KX-1GP
C2041 SCD1U10V2KX-5GP
C2034 SCD1U10V2KX-5GP
C2035 SC1U6D3V2KX-GP
L HCB2012KF-221T30-GP 1 1 1 1
H8 J8 K8 K9 M9 M10 N9 N10 M12 N12 M11
L 2 BLM15AG221SS1D-GP
C2044 SC2D2U10V3KX-1GP C2045 SCD1U10V2KX-5GP VDDAN_1.1V_USB VDDCR_1.1V_USB 2 1 C2080 SC2D2U10V3KX-1GP C2046 SCD1U10V2KX-5GP 1 C2047 SCD1U10V2KX-5GP
68.0nd = 68.
RR2J-2-GP 2 1
VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_11_USB_S VDDAN_11_USB_S VDDCR_11_USB_S VDDCR_11_USB_S VDDAN_11_SSUSB_S VDDAN_11_SSUSB_S VDDAN_11_SSUSB_S VDDAN_11_SSUSB_S VDDAN_11_SSUSB_S VDDCR_11_SSUSB_S VDDCR_11_SSUSB_S VDDCR_11_SSUSB_S VDDCR_11_SSUSB_S
VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDXL_33_S VDDCR_11_S VDDCR_11_S
N18 L19 M18 V12 V13 Y12 Y13 W11 G24 N20 M20 J24 M8 AA4
C2036 SC2D2U10V3KX-1GP
If support USB 3.0 or LAN wake-up, pls tie to 3.3V_S5 otherwise, tie to 3.3V_S0 220 ohm 300mA
RR2J-2-GP 2 1 1D1V_S5 1D2V_S5 2 C2042 SCD1U10V2KX-5GP 2 C2043 SC2D2U10V3KX-1GP 3D3V_S5 L BLM15AG221SS1D-GP
5mA 190mA 70mA 12mA 26mA
VDDXL_3.3V
1D1V_S5 1D2V_S5
VDDCR_1.1V_B
DY 2 RJ-2-GP
68.0nd = 68.
SC1U6D3V2KX-GP
220 ohm 300mA
L DY BLM15AG221SS1D-GP
VDDPL_11_SYS_S VDDAN_33_HWM_S VDDIO_AZ_S
1D1V_VPPL_SYS_S5 2 3D3V_VDDAN_HWM_S5 3D3V_S5 1 C2059 SC1U6D3V2KX-GP
C2049 SC1U6D3V2KX-GP
M14 N14 P13 P14 VDDAN_1.1V_SSUSB_S
DY 33 ohm 3A
L PBY0Y-N-GP 1
N17 P17 M17
220 ohm 300mA
3D3V_USB_S5 1 3D3V_VDDPL_USB_S5 L2013 2 BLM15AG221SS1D-GP 2 C2060 SC2D2U10V3KX-1GP 1 2 C2061 SCD1U10V2KX-5GP
C2054 SC1U6D3V2KX-GP
C2055 SCD1U10V2KX-5GP
C2056 SCD1U10V2KX-5GP
71.HUDM2.M03
If support USB 3.0 wake-up, tie to 1.1V_S5 If no, tie to 1.1V_S0, If no USB 3.0, tied to GND
3D3V_S0 3D3V_VDDPL_MLDAC_S0 1 R2-PAD 2 1 C2062 SC2D2U6D3V3KX-GP 1 C2063 SCD1U10V2KX-5GP
C2050 SCD1U10V2KX-5GP
C2051 SCD1U10V2KX-5GP
C2052 SC1U6D3V2KX-GP
Codec power use3.3V,VDDIO_AZ have to tied to 3.3V Codec power use1.5V,VDDIO_AZ have to tied to 1.5V If use 1.5V_S5 power,have to add LDO for it extra
68.0nd = 68.
VDDCR_1D1V
DY 2 RJ-2-GP
68.0nd = 68.
220 ohm 300mA
3D3V_S0 3D3V_VPPL_SYS_S0 L BLM15AG221SS1D-GP
220 ohm 300mA
3D3V_S5 1 2 1 C2058 SCD1U10V2KX-5GP 3D3V_VDDAN_HWM_S5 L2015 2 BLM15AG221SS1D-GP 2 1
220 ohm 300mA
1D1V_S5 1D1V_VPPL_SYS_S5 L BLM15AG221SS1D-GP C2074 SC2D2U10V3KX-1GP C2064 SCD1U10V2KX-5GP 1D2V_S5
220 ohm 300mA
3D3V_VDDPL_SSUSB_S5
68.0nd = 68.
SCD1U10V2KX-5GP
L BLM15AG221SS1D-GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
C2057 SC2D2U10V3KX-1GP 2
68.0nd = 68.
68.0nd = 68.
68.0nd = 68.
C2066 SC2D2U10V3KX-1GP
HW Montior Not implemented or HW Montior balls not used GPIO =& Decoupled cap not used
3D3V_VDDAN_DAC_S0_R
68.0nd = 68.
If USB 3.0 wake-up is supported, tie to 3.3V_S5 If no, tie to 3.3V_S0, If no USB 3.0, tie to GND
L2018 2 BLM15AG221SS1D-GP
2 C2072 SC2D2U10V3KX-1GP 1 C2071 SCD1U10V2KX-5GP
HW Montior Not implemented or HW Montior balls used as GPIO =& Bead not used
If support USB 3.0, tie to 1.1V_S5 otherwise, tie to 1.1V_S0
68.0nd = 68.
L BLM15AG221SS1D-GP
&Variant Name&
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
HUDSON-M2(4/6)
Size A2 Date:
Document Number Friday, April 01, 2011
SSID = S.B
CRB:PU 3.3V_AUX_S5
REQUIRED STRAPS
checklist:PU 3.3V_S5 no support S5 PLUS funciton,PU 3.3V_S5
REQUIRED SYSTEM STRAPS
USE this pin to determine INT/EXT CLK
RTC_CLK CLK_PCI_LPC USE DEBUG STRAPS PCI_CLK4
PCH GPO199 PULL HIGH
PCI_CLK1 Allow PCIE GEN2
CLKGEN ENABLED (Use Internal)
S5_PLUS Mode DISABLE
non_Fusion CLOCK mode
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
Force PCIE GEN1
S5_PLUS Mode ENABLE
IGNORE DEBUG STRAPS
Fusion CLOCK mode
DISABLE EC
CLKGEN DISABLED (Use External)
17 PCI_CLK1 17,65,71 CLK_PCI_LPC 17 PCI_CLK4
LPC ROM implemented checklistsuggestion: no PU or PD required
17,27 LPC_CLK0 17 LPC_CLK1 18 17 EC_PW M2 RTC_CLK R R R RR2F-GP
(integrated PU 10K) CRB: do not stuff PU Res
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
10KR2J-3-GP
DEBUG STRAPS
PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 17 17 17 17 17
PCI_AD27 PULL HIGH
USE PCI PLL (DEFAULT)
Disable ILA AUTORUN (DEFAULT)
USE FC PLL (DEFAULT)
USE DEFAULT PCIE STRAPS (DEFAULT)
Disable PCI MEM BOOT (DEFAULT)
DY DY DY DY DY
2K2R2J-2-GP 2K2R2J-2-GP 2K2R2J-2-GP 2K2R2J-2-GP 2K2R2J-2-GP
BYPASS PCI PLL
Enable ILA AUTORUN
BYPASS FC PLL
USE EEPROM PCIE STRAPS
Enable PCI MEM BOOT
&Variant Name&
Note: FCH has 15K internal PU FOR PCI_AD[27:23]
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
HUDSON-M2(5/6)
Size A3 Date:
Document Number Friday, April 01, 2011
Part 4 of 5
A3 A33 B7 B13 D9 D13 E5 E12 E16 E29 F7 F9 F11 F13 F16 F17 F19 F23 F25 F29 G6 G16 G32 H12 H15 H29 J6 J9 J10 J13 J28 J32 K7 K16 K27 K28 L6 L12 L13 L15 L16 L21 M13 M16 M21 M25 N6 N11 N13 N23 N24 P12 P18 P20 P21 P31 P33 R4 R11 R25 R28 T11 T16 T18 N8 K25 H25
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSAN_HWM VSSXL VSSPL_SYS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPL_DAC VSSAN_DAC VSSANQ_DAC VSSIO_DAC EFUSE
T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33 T21 L28 K33 N28 R6
71.HUDM2.M03
&Variant Name&
Wistron C}