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边界器件BSDL描述在测试中的应用
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封装测试技术
边界扫描器件BSDL描述在测试中的应用
王宁 ，李桂祥 ，张尊泉
(1.空军雷达学院研究生队,湖北 武汉 .空军雷达学院雷达系统工程系，
湖北 武汉 .空军雷达学院改装训练系，湖北 武汉 430019)
摘要：在对描述器件边界扫描特性的BSDL语言进行了深入研究之后，将其应用于边界扫描自动测试
图形生成ATPG与故障诊断软件中。本文以EPM7128SL84芯片为例，说明了其BSDL描述在边界扫描测
试程序中的应用方法与要点。
关键词：边界扫描；边界扫描描述语言；BSDL；测试
中图分类号： TP312;TP333.5文献标识码：A
文章编号：
in boundary-scan test
WANG ning，LI Gui-xiang，ZHANG Zun-quan
(1.Group of Graduates，Air Force Radar Academy，Wuhan430019 China)
(2.Department of Radar System Engineering，Air Force Radar Academy，Wuhan430019 China)
，Wuhan430019China)
ary-scan device EPM7128SL84.
Key words:
IEEE1149.1标准文件的附件。BSDL本身不是一种通
用的硬件描述语言，但它可与软件工具结合起来用
“边界扫描”是一种可测性设计技术，即在电
于测试生成、结果分析和故障诊断。每一边界扫描
器件都附有特定的BSDL描述文件，为了论述的方
子系统的设计阶段就考虑其测试问题 。
BSDL（boundary scan description language）
便，本文将以Altera公司的CPLD器件EPM7128SL84
语言硬件描述语言 （VHDL）的一个子集，是对边
芯片为例说明BSDL描述在测试中的应用。
界扫描器件的边界扫描特性的描述，主要用来沟通
EPM7128SL84芯片的BSDL描述
边界扫描器件厂商、用户与测试工具之间的联系，
其应用包括：厂商将BSDL描述作为边界扫描器件
该器件采用了先进的CMOS EEPROM制造工
的一部分提供给用户；BSDL描述为自动测试图形生
艺，共有84个引脚，其中包括四个JTAG测试引脚
成 （ATPG）工具测试特定的电路板提供相关信
TDI、TMS、TCK和TDO，通过标准JTAG测试
息；在BSDL的支持下生成由IEEE1149.1标准定义
接口它还可以支持在系统可编程 （ISP）。下面首
先讨论EPM7128SL84的BSDL描述中与应用相关的
的测试逻辑 。现在，BSDL语言已经正式成为
半导体技术第28卷第10期
二OO三年十月
封装测试技术
各基本元素。
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关注微信公众号Accelerated scan circuitry and method for reducing scan test data volume and execution time
United States Patent Application
An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
Inventors:
Dervisoglu, Bulent (Mountain View, CA, US)
Cooke, Laurence H. (Los Gatos, CA, US)
Application Number:
Publication Date:
07/29/2004
Filing Date:
01/05/2004
Export Citation:
On-Chip Technologies, Inc. (Los Gatos, CA)
Primary Class:
International Classes:
G01R31/3183; G01R31/3185; (IPC1-7): G01R31/28
View Patent Images:
&&&&&&PDF help
Related US Applications:
October, 2008Dorai et al.November, 2008Gemmeke et al.September, 2009Mooney et al.June, 2006Shrader et al.April, 2007RothDecember, 2006Milne et al.December, 2007Belady et al.May, 2009ValadonDecember, 2008Romero et al.August, 2006Bedi et al.September, 2002Doane
Attorney, Agent or Firm:
VENABLE, BAETJER, HOWARD AND CIVILETTI, LLP (P.O. BOX 34385, WASHINGTON, DC, , US)
1. A method for computing compressed serial scan-in values for a scan-chain, said method comprising: beginning with a desired scan-chain state as an initial current scan-chain state, said desired scan-chain state comprising one or more care-in values and zero or more don't-care values, repeatedly computing a previous scan-chain state and serial scan-in input value that must have existed one shift cycle prior to said current scan-chain state and setting said previous scan-chain state as the said current scan-chain state, until said current scan-chain state has pre-determined values in pre-determined bit positions of said scan- and forming said compressed serial scan-in values from said computed serial scan-in input values.
2. A method as described in claim 1, wherein said compressed serial scan-in input values are generated using a data spreading network that receives a multiplicity of external serial input values that are used to generate a greater number of said serial scan-in input values than said multiplicity of external serial input values.
3. A method as described in claim 1, where said scan-chain comprises a multiplicity of scan-chain segments, wherein inserting serial data into said scan-chain segments is performed by combining a next bit value of said serial scan-in input and a multiplicity of present values of scan-chain bit positions previous to the first bit positions of said scan-chain segments.
4. A method as described in claim 3, wherein said compressed serial scan-in input values are generated using a data spreading network that receives a multiplicity of external serial input values that are used to generate a greater number of said serial scan-in input values than said multiplicity of external serial input values.
5. A method of testing an integrated circuit comprising at least one scan-chain, at least one said scan-chain comprising a multiplicity of scan-chain segments, said method comprising: loading at least one of said at least one scan chain using compressed serial scan-in values determined according to the method of claim 4.
6. A method as described in claim 1, wherein said forming comprises: taking said computed serial scan-in input values in reverse order.
7. A method of testing an integrated circuit that contains scan-chains using compressed scan-chain patterns, wherein at least one of said compressed scan-chain patterns is computed according to the method of claim 1.
8. A method to compute compressed sequences of values for decompression by a data spreading network, said method comprising: starting with sequences of don't care and care-in values desired to be produced by said data-spreading network, applying successive values from said sequences of don't care and care-in values to the outputs of said da resolving values on the inputs of said data spreading network associated with said outputs of said data spreading network, to pro and forming said compressed sequences of values as compressed sequences from said resolved values.
9. A method as in claim 8, wherein said resolving values on the inputs of said data spreading network comprises: generating one or more symbolic expressions associated with said inputs, said one or more symbolic expressions being formed as functions of input variables and said successive values applied to the outputs of said da and resolving values of said input variables and said one or more symbolic expressions.
10. A method as in claim 8, wherein said resolving values on the inputs of said data spreading network comprises: generating one or more symbolic expressions associated with said inputs and a set of one or more state variables that represent an internal state of said data spreading network, said one or more symbolic expressions being formed as functions of one or more of the following: said successive values applied to the outputs of said da and present values of said one or
replacing present values of said one or more state variables with symbolic expressions associated with said one or
and resolving values of said input variables and said symbolic expressions.
11. A method for loading a scan-chain, said scan-chain comprising a multiplicity of scan-chain segments, said method comprising: inserting pseudo-random serial data into at least one of said scan-chain segments, said inserting including applying a combination of a next bit value of said pseudo-random serial input data and a multiplicity of values of scan bit positions previous to first bit positions of said scan-chain segments.
12. A method of testing an integrated circuit comprising at least one scan-chain, at least one of said at least one scan-chain comprising a multiplicity of scan-chain segments, said method comprising: loading at least one of said at least one scan chain according to the method of claim 11.
13. A scan flip-flop, a Scan_I a Data_I a Scan_E a CLK a Data_O and having a means to: capture data from said Data_In port in one state of a signal on said Scan Enable port by applying a change to signal on said CLK port thereby changing it to a pre-defined CLK capture data from said Scan_In port in a different state of the signal on said Scan_Enable port by applying said change to signal on said CLK port thereby changing it to said pre-defined CLK disable loading data from either of said Scan_In port and said Data_In port in said pre-defined state of signal on said CLK and use a combination of states of signals on said Scan_Enable port and said CLK port to enable reflecting said captured data at said Data_Out port, said reflected data on said Data_Out port being held constant at other times.
14. A circuit structure comprising: a multiplicity of scan-chains, wherein at least one of said scan- a multiplicity of flip-flops as described in claim 13, at least one said Scan_Enable port of at least one said flip-flop being coupled to a control signal wherein: in one state, said control signal provides information to select operation of said flip-flop responsive to said Scan_In port or responsive to said Data_I and in another state, said control signal provides information to select operation of said flip-flop to reflect said captured data at its Data_Out port.
15. A method of distributing a control signal for a scan-chain that receives a clock signal having at least two states, the method comprising: using said control signal to carry information to select operation of said scan-chain between a system mode of operation and a scan mode of operation when said clock signal using said control signal to carry information to select between updating said scan-chain with new data values and leaving present data values in said scan-chain unchanged when said clock signal is in a second state.
16. A structure for controlling a multiplicity of clocks, comprising: and a common clock, wherein said structure enables the said common clock to generate each of the multiplicity of wherein the structure implements a mode to enable all the multiplicity of clocks in one state of said control input and a mode to successively enable each one of the multiplicity of clocks in one state of the count input.
17. A circuit structure as in claim 16, further comprising: and a multiplicity of scan chains, each clocked by one of said mu wherein a multiplicity of data values from said data input is successively scanned into each one Of said multiplicity of scan chains, one scan chain at a time.
18. An integrated circuit (IC), comprising: a multiplicity of mode-control signals, each adapted to assume one of a multiplicity of scan-chains, each comprising at least one flip- a multiplicity of blocking circuits, each of said multiplicity of blocking circuits receiving at least one data-in signal and adapted to be responsive to at least one said mode-control signal, each of said multiplicity of blocking circuits providing serial scan data to at least one flip-flop of said multiplicity of scan- wherein each of said blocking circuits outputs a value that is representative of a combination of a value on said at least one data-in signal of said blocking circuit and at least one value of at least one scan bit position previous to said at least one flip-flop, in at least a first state of said multiplicity of and each of said blocking circuits outputs a constant value, in at least a second state of said multiplicity of mode control inputs.
19. The integrated circuit according to claim 18, further comprising: a multiplicity of multi-input signature register (MISR) blocks that are adapted to be responsive to a multiplicity of outputs of said multiplicity of blocking circuits.
20. The integrated circuit according to claim 18, wherein each of said blocking circuits comprises: a multiplexer adapted to be responsive to at least one said mode- a logic gate adapted to be coupled to a first data input of said multiplexer, said logic gate adapted to receive as inputs at least one data-in signal and at least one additional input from a scan bit position previous to said at least one flip-flop.
21. The integrated circuit according to claim 21, wherein said at least one additional input from a scan position previous to said at least one flip-flop is coupled to at least a second data input and wherein said multiplexer is adapted to produce an output value that is representative of a signal value at said first data input in a first state of said mode- and wherein said multiplexer is adapted to produce an output value that is representative of signal value at said at least a second data input in a second mode of said mode-control signal.
22. The integrated circuit according to claim 18, further comprising: a multiplicity of multi-input signature register (MISR) blocks, wherein each of said MISR blocks is prevented from capturing “X” states from a multiplicity of tap points on said scan chain when one or more of said tap points contain said “X” state.
23. An apparatus for eliminating “X” states within a scan chain, the apparatus comprising: one or more blocking circuits adapted to selectively replace propagated states with known states when one or more of said “X” states are propagated from one flip-flop of said scan chain to a next flip-flop of said scan chain through said blocking circuits.
24. A boundary scan flip-flop comprising: a data- a data- a scan- a scan- a probe- a probe- and a flip- wherein said ports and said flip-flop are adapted to implement at least: a system operation mode, enabled by one state of said test port, wherein said boundary scan flip-flop propagates a signal from said data-in port to said data-out port, and selects between propagating a signal from said probe-in port and said data-in port based on a state of said flip- and a test operation mode, enabled by a different state of said test port, wherein said boundary scan flip-flop propagates a signal from said probe-in port to said probe-out port, and captures a signal on said data-in port for shifting out through said scan-in and scan-out ports.
25. The boundary scan flip-flop as in claim 24, further comprising: a first multiplexer adapted to be coupled to said data-in port and to said flip-flop, an output of said first multiplexer adapted to be coupled to said data-out port, the first multiplexer adapted to be responsive to a signal and a second multiplexer adapted to be coupled to said probe-in port and to said data-in port, an output of the second multiplexer adapted to be coupled to said probe-out port, the second multiplexer adapted to be responsive so said signal from said test port.
26. The boundary scan flip-flop as in claim 25, further comprising: a logic gate coupled to said flip-flop and to said test port, an output of said logic gate adapted to provide a select input to said second multiplexer.
27. A multiplicity of boundary scan flip-flops as in claim 24, connected to form a multiplicity of boundary scan chains, wherein at least one of said boundary scan-chains contains a multiplicity of scan segments such that any data in port of any boundary scan flip-flop may be probed during system operation.
28. A multiplicity of boundary scan flip-flops as in claim 27, wherein at least one compressed test pattern is used during said test operation mode.
29. An integrated circuit (IC), comprising: a multiplicity of p and a multiplicity of scan- wherein at least one of said multiplicity of scan-chains comprises multiple scan-chain segments, each of said multiple scan-chain segments having a segment serial input, wherein said segment serial inputs to a multiplicity of subsequent ones of said multiple scan-chain segments are determined as at least one function of said primary serial inputs combined with a multiplicity of scan positions of a multiplicity of previous ones of said multiple scan-chain segments.
30. A machine-readable medium that provides instructions that, when executed by a computing platform, cause said computing platform to perform operations comprising the method according to claim 1.
31. A machine-readable medium that provides instructions that, when executed by a computing platform, cause said computing platform to perform operations comprising the method according to claim 8.
Description:
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10/351,276, entitled “VARIABLE CLOCK SCAN TEST CIRCUITRY AND METHOD,” filed on Jan. 24, 2003, commonly assigned, and incorporated herein by reference.FIELD OF THE INVENTION [0002] The present invention is related to digital logic testing, particularly additions to scan based digital logic testing, which uses check-sum or signature register logic and exclusive-OR operations on serial shift string logic, and software techniques to reduce test data volume and minimize test time. BACKGROUND AND SUMMARY OF THE INVENTION [0003] Scan-based testing, as described in as described by Eichelberg in U.S. Pat. No. 3,784,907, and Zasio et al. in U.S. Pat. No. 4,495,629, has been the staple of Design for Testability methodology for over 30 years. The technique drives its strength from its ability to replace the state variables (i.e. flip-flops) that make up a sequential circuit by pseudo inputs and outputs whose values can be set arbitrarily or be observed by connecting the memory elements in a serial shift register configuration. Since serial shift (i.e. scan) actions can be employed to set the flip-flops of the Circuit Under Test (CUT) to any arbitrary set of values, the process transforms a sequential circuit into a virtual combinational circuit where Scan_In and Scan_Out activities are defined as macro operations to set (i.e. control) and observe the state variables of the CUT. Using this methodology, Scan_In is performed to apply the inputs at the pseudo-input pins of the CUT, followed by a Capture operation, which captures the response of the CUT to the input values. Next, Scan_Out is employed to read out the captured results at the memory elements that are used to implement the state variables. Furthermore, Scan_Out of the captured test results for a previous test can be overlapped with the Scan_In of the input values for the next test in order to reduce some of the time overhead of scan-based testing. [0004] As scan technology has enabled transforming the problem of sequential test pattern generation into the much easier problem of test pattern generation for a combinational circuit it has led to the development of very efficient combinational ATPG algorithms. However, with increasing circuit complexity, which is often measured in terms of the number of state variables (i.e. flip-flops or latches used to implement it) the total number of serial bits that have to be scanned in and out in serial fashion has become a problem. To combat this problem, designers have reverted to implementing parallel scan whereby the overall scan chain is broken into a number of independently operable serial scan chains so that the effective serial scan overhead can be reduced by a factor that is equal to the number of parallel scan chains. For example, a 100,000-bit serial scan chain may be implemented as 10, independently operable scan chains of 10,000 bits each and thereby reduce the total number of shift cycles necessary to load/unload all of the 100,000 bits by a factor of 10. [0005] Parallel scan can help alleviate some of the serial scan, but test time issues limit its effectiveness to the number of independently operable scan chains that can be implemented on a target Integrated Circuit (IC). Each independent scan chain requires a pair of Scan_In/Scan_Out pins that are directly accessible using the primary I/O pins of the IC. Most IC's are limited by the number of their I/O pins that are available for scan and other test purposes. Parallel scan can be implemented using a sharing of some of the primary I/O pins between their functional and Scan roles. Unfortunately, shared I/O pins impact the target IC's maximum operating speed. Furthermore, it is not possible to take advantage of parallel scan unless the Automatic Test Equipment (ATE) that will be used to test the target IC has the ability to feed and observe data on the parallel scan channels simultaneously. As might be expected, often the ATE imposed limit on the independently operable scan chains is more severe than the limit imposed by the target IC designer. In addition to its limitations as described above, parallel scan, does not address a crucial issue. Whether a single, serial scan or an n-channel parallel scan architecture is used, the total number of bits of data that need to be scanned-in and scanned-out for each ATPG vector remains the same. Today, it is not unreasonable to expect a complex IC to contain close to 1M flip-flops that are scanable. Considering that for each ATPG vector we may need an input vector, an (expected) output vector, and (possibly) a mask vector to indicate whether an output bit value may be used reliably, 2K×1M× 3/8 :=750 MB of high-speed ATE memory may be required to hold all of the test patterns and the expected results. The total volume of test related data and the need for increased physical bandwidth (i.e. number of externally controllable parallel scan chains) are fast becoming dominant factors in determining overall test cost of complex ICs. The concerns described above have made it desirable to reduce the total data volume needed for scan-based ATPG. To this end, a crucial observation has been made that for any given ATPG vector only a very small percentage of the total number of scanable bits are needed to be set to
the vast majority of the scanable bits are free and can be (are) set to pseudorandom values to achieve additional incidental fault coverage. The ATPG program sets these bits to logic 1 or logic 0 values, but their specific values are not critical and another set of pseudo random values may also be employed without any appreciable change in fault coverage. This observation has led to the development of techniques that focus on data compression of the scan vectors whereby the pre-determined bit values are preserved while the pseudo random values can be filled in a manner to achieve greater data compression. For example, U.S. Pat. No. 6,327,687, by Rajski et al. describes such a technique. [0006] The primary goal in test data compression for scan-based testing using ATPG vectors is to store sufficient information off the chip (i.e. on the ATE) that allows setting pre-determined bit positions of each scan vector to their ATPG-determined values while setting the remaining bit positions to values that aid in maximum data compression. Characteristic of all state-of-art techniques to achieve this is that they achieve their objective while length (i.e. number of clock cycles) for the scan operations remains unchanged before and after test data compression. This has been deemed necessary since scan in of input values for the present test vector is overlapped with scan out of test results from the previous test vector such that the two leng Extending this requirement over the entire test vector set is achieved by keeping the scan-length be constant over the entire test set. In this case, reduction of scan test data volume can only be achieved by scanning a seed value into a data decompressor network that receives the shorter-length seed values in order to produce the actual values to be fed into the scan chains. Typically, the decompressor network is based on an LFSR which is implemented inside the target device under test (DUT) and a set of simultaneous EXOR-equations need to be solved to determine the seed values to be fed into the LFSR circuit during test. [0007] A recent U.S. patent application Ser. No. 10/351,276, filed Jan. 24, 2003, describes a different approach that is based on a technique whereby the hereto unquestioned overlapping of the scan-in and scan-out operations is considered separately from each other. One aspect of the new technique is driven by the observation that, even after compaction, only a very a small percentage (less than 2%) of bit values of each ATPG-generated scan-test vectors are set to pre-determined values (called Care_In values) while the remaining bits are set to pseudorandom values with hopes of achieving increased incidental coverage. In similar fashion, Care_Out positions are defined as bit positions along a scan-chain that contain pre-determined test results that are indicative of the pass/fail nature of tests executed by previous test vector. Similar to the small number of Care_In positions for each test vector, there are only a small percentage of Care_Out positions for each given result vector. Separation of the scan in and scan out operations from each other enables using this fact in reformulating the scan in problem as: [0008] Given the present-state of values along a scan chain, find an efficient way to set all Care_In positions to pre-determined values without concern about values achieved in other, non-Care_In bit positions. Similarly, the scan out problem can be reformulated as: [0009] Given the set of test results along a scan chain, find a cost-efficient structure to observe all of the Care_Out values, either directly or using a MISR. [0010] As with the previous U.S. patent application Ser. No. 10/351,276, filed Jan. 24, 2003, a unique advantage of the present invention is, the separation of Scan_In and Scan_Out problems from one another, which leads to a very effective solution to the problem of reducing data volume and test time for scan-based testing of IC's. The present invention extends the previous Application, with improved methods for computing such compressed test vectors and with improved circuitry that eases its implementation in hardware. [0011] While reading the remainder of the descriptions, it is useful to focus on number of cycles for the Scan_In and Scan_Out operations, in the remainder of this patent, the inventors are using this terminology as a semaphore for the volume of test-related data since, for a given number of externally accessible Scan_In/Scan_Out ports, a smaller number of scan cycles implies less data volume.BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 shows a sample scan-chain that uses the usual pair of Scan_In and Scan_Out ports as well as using additional output taps from several positions along the scan-chain to feed data into a Checksum or Multi Input Signature Register (MISR). [0013] FIG. 2 shows an example to demonstrate opportunistic scan whereby present values along the scan-chain may become used in achieving desired values in all of the Care_In positions while other non-Care_In positions may be set to some other values. [0014] FIG. 3 shows an example of an embodiment for a multi-segmented scan-chain where each successive scan-segment is coupled to the previous segments using exclusive-or (EXOR) gates that use the common serial input value and the value from the last bit of the previous segment to be used as serial input to the first bit position of the next segment. [0015] FIG. 4 shows multiple cycles of operation using a multiple-segmented scan-chain, which is used with opportunistic scan to achieve desired values in the Care_In positions. [0016] FIG. 5a shows the initial state for an example that uses a 4-segmented scan-chain and shows the desired Care_In values that are intended. FIGS. 5b through 5f shows the scan-chain values after each of the next 5 shift cycles. FIG. 5c shows the scan-chain value after the second shift cycle. FIG. 5d shows the scan-chain value after the third shift cycle. FIG. 5e shows the scan-chain value after the fourth shift cycle. FIG. 5f shows the scan-chain value after the fifth shift cycle and shows that the desired Care_In values have been achieved. [0017] FIG. 6a shows the same example as used in FIG. 5a but uses symbolic values applied at the Scan_In port and shows the next state of the scan-chain after 1 shift cycle. FIG. 6b shows the scan-chain state after 2 shift cycles. FIG. 6c shows the scan-chain state after 3 shift cycles and demonstrates how a new symbolic variable is introduced into the scan-chain while also generating and recording an EXOR equation that will have to be solved in order to find a valid solution. FIGS. 6d and 6e shows the scan-chain state after 4 shift cycles and 5 shift cycles, respectively, and shows the EXOR equations that have been generated. FIG. 6e shows the scan-chain in FIG. 6d after the next shift cycle. FIG. 6e shows the scan-chain state after 5 shift cycles along with all of the EXOR equations that have been generated. This example demonstrates that setting the symbolic values so that A=0, B=1, C=1, D=0, E=1 satisfies the conditions represented by the EXOR equations as well as achieving the desired values in the Care_In positions. Therefore, the 5-bit serial input sequence of E, D, C, B, A=1, 0, 1, 1, 0 (value for A is fed into the scan-chain first) achieves the Care_In values in the 10-bit long scan-chain. [0018] FIG. 7a shows what the previous state of the scan-chain should have been in order that one shift cycle later the desired present state of the scan-chain is obtained, which is the first step in the preferred and more efficient algorithm for computing the compressed sequence by starting from the desired scan-chain state and going backwards in time to compute the required previous state, until the computed previous state matches the known starting state of the scan-chain. FIG. 7a shows the desired scan-chain state where only the Care_In values are specified and all other bits are set to Don't_Care values. FIG. 7a also shows what the previous state of the scan-chain should have been in order that once shift cycle later the desired present state of the scan-chain is obtained. FIGS. 7b through 7e shows the computed previous scan-chain state for reverse-shift of cycles 2 through 5 of the preferred algorithm. FIG. 7b shows the computed previous scan-chain state for reverse-shift of 2 cycles of the preferred algorithm. FIG. 7c shows the computed previous scan-chain state for reverse-shift of 3 cycles of the preferred algorithm. FIG. 7d shows the computed previous scan-chain state for reverse-shift of 4 cycles of the preferred algorithm. FIG. 7e shows the computed previous scan-chain state for reverse-shift of 5 cycles of the preferred algorithm, and FIG. 7e also shows that using only two symbolic variables (A and B) and without generating any EXOR equations to be solved, the reverse-shift algorithm discovers the same 5-bit compressed Scan_In sequence for the same example demonstrated in FIG. 6. [0019] FIG. 8 shows an example of a situation where a new symbolic variable may be introduced into the scan-chain and an EXOR equation may be generated when using the reverse-shift algorithm. [0020] FIG. 9 shows an example of using present invention with multiple, parallel scan-chains each of which may have multiple scan segments of differing lengths. [0021] FIG. 10a shows an embodiment of a logic circuit, as described in the previous U.S. patent application Ser. No. 10/351,276, filed Jan. 24, 2003, that can be used to start and stop the scan-clock for a scan-chain using the values that are applied to the Scan_In port of that scan-chain. FIG. 10b shows an improvement over the circuit of FIG. 10a, with serialization of compressed scan-in data. [0022] FIG. 11 shows a data spreading network that takes in serial data along Scan_In ports Si1 through SiK and expands these to drive its output ports Sol through SON (N&K) so that only K-many Scan_In ports can be used to provide serial data for N-many parallel scan-chains, where one or more of the parallel scan-chains are implemented using the multiple-segmented scan-chain architecture. [0023] FIG. 12 illustrates including the Automatic Test Equipment (ATE) in the compression loop so that first an ATE-run process is executed in hardware or software (1204) to generate compressed scan-in sequences that are provided as serial inputs to the target IC (1201) whereby on-chip EXOR gates among the segments of the internal scan-chains are used to set the Care_In values as required by each original test vector. [0024] FIG. 13 illustrates three different techniques for controlling the clocking of the individual scan-chains that are operated in parallel. FIG. 13a shows the preferred embodiment of a technique for controlling the clocking of the individual scan-chains that are operated in parallel using a common Scan_Enable signal 1007 and individual clocks 1301 to control the separate scan-chains. [0025] FIG. 13b illustrates another preferred embodiment of a technique for controlling the clocking of the individual scan-chains that are operated in parallel, using a common Scan_Enable signal 1007 and individual clock control circuits 1010 to generate gated clocks 1009. FIG. 13c shows another technique that uses the preferred embodiment of a flip-flop shown in FIG. 14 as well as showing how to connect multiple flip-flops of the shown type together to form a single scan-chain. [0026] FIG. 14 shows a preferred embodiment for the design of a flip-flop that uses the SE/CLKA port to receive a common control signal that can be used as the Scan_Enable signal as well as CLKA signal to perform scan operation. [0027] FIG. 15a shows an example that demonstrates using a modified version of the clock-control circuit shown in FIG. 10 together with the flip-flop illustrated in FIG. 14 so that a common clock signal can be shared among multiple scan-chains operating in parallel. FIG. 15a shows the preferred embodiment of a circuit that generates the SE/CLKA signal for use by the flip-flops as well as showing how to connect multiple flip-flops together to form a single scan-chain. FIG. 15b shows a timing diagram for the operation of circuit in FIG. 15a. FIG. 15c shows a modified control signal that incorporates a functional Enable control signal to control updating of individual flip-flops with new data during normal mode of operation. Test_Mode signal (1508) is used to disable the affect of the functional enable control signal (1510) when the circuit is placed in a test mode so that scan operations may be possible. [0028] FIG. 16a shows an embodiment that uses blocking circuits to prevent unknown (“X”) values from spreading into a MISR and to purge them out of the existing scan-chain. FIG. 16b shows the details of a blocking circuit that may be used in FIG. 16a. [0029] FIG. 17a shows an embodiment of a boundary scan flip-flop. FIG. 17b shows a preferred embodiment that includes the boundary scan flip-flop, shown in FIG. 17a, between scan segments in the boundary scan chain. [0030] FIG. 18 shows an alternative embodiment of at least some aspects of the invention.DESCRIPTION OF SPECIFIC EMBODIMENTS [0031] Traditional approach to scan-based testing employs overlapped Scan_Out of the results for the most recently executes test pattern with the Scan_In for the next test pattern. The primary motivation for doing so has been to take advantage of the ability to feed new serial data (i.e. next test pattern) at one end of the scan-chain while simultaneously receiving the results for the previous test pattern since the two serial streams are of equal length. However, scan-out bits do not all contain useful information regarding the pass/fail status of the previous test vector. Indeed, the only bits where useful information is present are bit positions where at least one fault effect has been propagated. Thus, it is only useful (necessary) to scan-out those bit positions that contain useful information. Here, those bits are referred to as Care_Out bits. It is noted that, typically, each test results vector may contain a small number of Care_Out bits. The remaining bits become set to specific values (0 or 1). These values may not carry any additional information about any faults in the circuit under test. Furthermore, Scan_Out of the Care_Out values can be speeded-up (i.e. the number of Scan_Out cycles can be reduced) by using multiple primary output pins where Scan_Out values can be observed in order to increase the Scan_Out bandwidth. These two concepts can be used together so that, in a preferred embodiment of the present invention, serial Scan_Out operations are continued until all Care_Out bits have been observed at least at one primary output pin. Scan_Out values observed at multiple pin positions can be combined using a checksum circuit whose output reflects the overall (composite) Scan_Out value for the given scan-chain. Alternately, the multiple output pins may be connected to a Multi-Input Signature Register (MISR) where they contribute to an overall signature value, which can be read out at a later point in time. This is illustrated in FIG. 1. [0032] While the Scan_Out values are being scanned-out, other bits of the scan chain will also be observed and reflected either in the checksum or in the MISR. For example, consider the case where the results vector contains a first Care_Out bit position (not necessarily the first bit position along the scan-chain) and a last Care_Out bit position (not necessarily the last bit position along the scan-chain) where test results information is present. In one approach, scan-out operations may be continued until all scan bits between the Serial_In and Serial_Out (i.e. the first and the last bit positions) have been observed at least on one primary output pin. In this case, the number of shift cycles needs to be at least as large as the total number of bits along the scan register and upon completion of the scan operations all bits along the scan register shall have been observed. In another approach, the scan-out process may be stopped at any time after all Care_Out bits for the present results-vector have been observed on at least one primary output pin. In this case the number of shift cycles needs to be larger than the positional difference between the last Care_Out bit and the first Care_Out bit so that not all bits of the scan-chain may have been observed before serial shifting is stopped. However, since all Care_Out bits have been observed, no loss of test data would occur due to skipping the other bits. Furthermore, the second approach may preferred since it may require fewer total number of shift cycles necessary to observe the test results. Traditional scan-based approaches have failed to take advantage of this property. One reason for this has been that since all bits need to be scanned-in for the next test vector (i.e. the Scan_In sequence) there is no advantage in not performing a complete scan-out of the previous test-results vector. The present invention describes a new scan architecture that does not require scanning pre-determined values into all of the scan positions. By eliminating the one-to-one overlapping of the Scan_In and Scan_Out present invention achieves superior data and time compression of scan-based test operation. [0033] It is well known to those experienced in IC testing methods that a vast majority of the input bits in scan-based test vectors are set to pseudorandom values during Automatic Test Pattern Generation (ATPG) that is typically executed using a standard Electronic Design Automation (EDA) tool. Stated in the reverse, for a given scan-based test vector, only a very small percentage of the scan-in bit positions are actually set to predetermined values. Typically, even after maximum test vector compaction, about 2% to 5% of the individual bit positions end up having been set to predetermined values. The remainders of the bit positions are set to pseudorandom values with hopes that these values may contribute to additional (incidental) fault coverage. Indeed, most ATPG tools offer the ability to fill these unselected bits to logic values that may help overall fault coverage, or that may reduce power dissipation during scan, or to help in data compression for the scan vectors. The unselected bit positions are also referred to as the Don't_Care positions. The present invention describes an approach that is aimed at taking advantage of the Don't_Care nature of the majority of the bit positions in order to fill all of the Care_In bit positions with their prescribed values by using as few serial shift cycles as possible. As part of this process, the Don't_Care bits will be set to certain values but there is no assurance that these values shall satisfy some characteristic, such as repeating values, mostly set to logic 0, Still, the present invention describes a method to satisfy the overall objective of setting all of the Care_In bit values to their prescribed values using as few shift cycles as possible. [0034] Using traditional serial scan, each bit position of the scan chain receives its next value from the present value of the previous bit position while the first bit receives its next value from the external Scan_In port. Therefore, one way to view the Scan_In operation is to focus on how to get the desired values into the previous bit positions so that they may subsequently be shifted upstream into the desired Care_In positions. For example, consider the case where the Care_In positions are equally spaced at, say, every 100th bit position along the serial scan chain. If, at some previous point in time, the present state of the serial scan chain is such that, say, the 13th, 87th, 187th, and so on, bit positions already contain the desired values (i.e. the Care_In values) for the 100th, 200th, 300th, and so on, bit position, then it will be known that 87 (100-13=87) more shift cycles are needed to set all of the Care_In positions to their desired Scan_In values. Ordinarily, the probability of success with such an opportunistic approach may not be very high. However, chances are improved when the number of Care_In positions becomes much smaller compared to the total number of bits along the serial scan chain. FIG. 2 illustrates this idea with an example. [0035] Traditional scan architecture requires Scan_In data to pass through all of the intervening bits between the Scan_In port and the final destination bit position during successive shift cycles. Thus, the total number of shift cycles necessary to load the last bit position (i.e. bit position that is farthest away from the Scan_In position) with the serial Scan_In data value determines the total shift count for all bits to be set to their final, desired values. An alternate scan structure is depicted in FIG. 3 where the overall serial scan-chain is broken into a number of serial scan segments and a common Scan_In signal (301) is used to affect the serial input into each of the multiple scan segments. The primary advantage of this scheme is that it allows the Scan_In value to bypass long sequences of successive bit positions (302, 305) between the Scan_In and the input to each scan segment. As shown in FIG. 3, this is achieved by merging the serial Scan_In value with the value from the last bit position from the previous scan segment using a combinational function, such as an Exclusive-Or (EXOR) gate (303). A useful property of the EXOR gate is that it implements an information lossless function that enables controlling the destination bit value through a combination of both the serial Scan_In and the value of the previous bit position. Since the previous bit positions themselves are determined by earlier values of the Scan_In signal, it is clear that the Scan_In value can be used to control all bit positions along the scan-chain. Thus, FIG. 3 represents a preferred embodiment of a characteristic of the present invention where successive scan segments are coupled together using an EXOR gate (303) where first input of the EXOR gate is connected to Scan_In (301) and second input of EXOR gate (303) is connected to output of last bit position (305) of previous segment. Indeed, it is not essential to limit this structure to using only the last bit position from the previous scan segment. Any number and combination of previous bits positions may be used to determine the value to be loaded into the serial input to the next segment of the scan-chain. Similarly, any other merging function can be used in place of the information lossless network that has been implemented using the EXOR function. However, using a common serial Scan_In value that is Exclusive-Or'ed (EXOR) with the last bit of the previous scan segment as the serial input to the next scan segment is preferred embodiment that is both simple and very effective. [0036] The goal in performing Scan_In operations is to set all Care_In positions along the scan chain to pre-determined values by feeding serial data from a pre-determined port, called the Scan_In port (301). This requires that an information lossless connection should exist between the Scan_In port and the bit positions (302, 305) along the scan chain. This is an essential requirement for any scan architecture since it makes it possible to load any combination of bit values into the scan-chain. Otherwise, any bit permutation that cannot be loaded into the scan-chain represents a test pattern that cannot be loaded into the scan-chain and thus cannot be applied to the Circuit Under Test (CUT). It is obvious that the traditional scan structure, implemented as an ordinary serial shift register, provides an information lossless path between the Scan_In port and any bit position along the scan-chain since all bit positions along the shift register can be loaded with the desired values by feeding these values in serial fashion to the scan-chain such that value desired at bit position “i” is applied to the Scan_In port during the “i-th” shift cycle. Even if there may be logic inversions along the scan-chain, knowledge of the number of logic inversions between the Scan_In port and the particular bit position enables counteracting the inversion effects by choosing also to invert or leave unchanged the Scan_In values at appropriate shift cycles. [0037] FIG. 4 demonstrates using a multiple-segmented scan-chain and taking advantage of opportunistic scan. In practice, scan-chains of much longer lengths are used, but for simplicity of explanations, FIG. 4 uses a single 6-bit scan-chain that has been broken into 2, equal-length (i.e. 3 bits each) scan segments that are coupled using an Exclusive-OR (EXOR) gate. It can be shown that, regardless of its starting state, the 6-bit scan-chain shown in FIG. 4 can be set to any arbitrarily selected values using at most 6 shift cycles. To see this, first, it is observed that the final set of values loaded into the first segment (S1) is the last three values applied at Scan_In. Thus, if it is desired that the scan-chain be loaded with binary values of 101011, the last three scan cycles should be executed with the Scan_In values set to 101. Furthermore, during the last 3 bits of scan, the previous values in segment S1 are Exclusive-Or'ed with the Scan_In values (i.e. 101) and loaded into the second segment (S2). Since the desired values in segment S2 are 011, and the incoming Scan_In values are 101, it follows that segment S1 must contain 011(+) 101=110 at the start of the last 3 scan cycles. In other words, 110 must have been scanned in during the first 3 shift cycles, to be followed by scanning in 101. This way, serial scan of 101110 will result in setting the scan-chain to 101011. In general, if it is desired to set the two segments to values S1 and S2, respectively, serial Scan_In vector must be set to values defined by S1, S2(+) S1. Since, S1 and S2 can be selected arbitrarily, this proves that any selection sets of values can be loaded into segments S1 and S2. [0038] The above analysis can be extended to the case where the serial scan-chain has been broken into more than 2 segments as well as having segments of unequal lengths and still show that any set of arbitrarily selected values can be loaded into the scan-chain without regard to its initial state and using no more than “n” shift cycles where “n” is the total number of bits along the entire scan-chain. A scan-chain that implements scan function with the above characteristics is termed complete. Furthermore, the analysis can be extended to show that this characteristic remains true even if the merging functions between the segments have been implemented using any number of bits from the previous segment that are fed into an information-lossless circuit whose output drives the input to the next segment. As long as all bit positions that feed into bit position “i” come before bit position “i” and their values (optionally also including the serial Scan_In value) are combined together using an information lossless circuit (such as an Exclusive-Or gate) the resulting Scan_In function remains complete. Traditional serial scan-chain implements a limiting case of the general complete scan function where the number of segments is equal to 1. [0039] For any scan-chain that is complete, in other words an information lossless path exists between the Scan_In port and any bit position along the scan-chain, it is not necessary to know the present state of the scan-chain in order to be able to set the scan-chain to an arbitrary new state using at most the number of Scan_In cycles that equals the length of the scan-chain, but a more useful characteristic of the scan architecture prescribed by the present invention is that it allows using the knowledge of the present state of the scan-chain in coming up with an even shorter length scan operation in order to load the Care_In values with desired (e.g. pre-determined) values. To see how this may be possible, first consider the normal (state-of-art) Scan_In operation and consider the state of the scan-chain just one cycle before completing the Scan_In operations. At that time, each present bit value will have been set to the desired target value of the next bit that follows it. In this case, a single shift cycle is all that is necessary to load all target values into their appropriate bit positions. Thus, if the state of the scan-chain one cycle prior to final, desired state is the same as the known starting state of the scan-chain, only a single bit of scan will be needed to load all bits with their final, desired values. The probability of such a situation arising in practice is small, but other considerations may ease the situation. First, given a scan-chain of “L” bits (i.e. having “L” bit positions), any shift sequence of length less than “L” to set all bits of the scan-chain to their desired values is preferred over full-scan, which requires exactly “L” shift cycles. Furthermore, not all bit positions of the scan-chain may need to be set to predetermined values. This will have a positive impact on the probability and length of a serial Scan_In sequence of fewer than “L” bits to set all Care_In bit positions with their targeted values. As stated earlier, scan-based ATPG algorithms typically generate test vectors where a small percentage of the bits represent Care_In values and the others are filled in random fashion. Obviously, the fewer the conditions that need to be met (i.e. the smaller the number of Care_In values that need to be set to predetermined values) the easier it is to set the scan-chain to a state where all Care_In positions have been set to their target. Additionally, and more importantly, bit positions, which are non-Care_In positions, can be set to the values that make them usable as input sources to set, at least some of, the Care_In positions. This is made possible due to the unique scan-chain architecture described here where each bit position may be used to control the values provided to other bit positions which are downstream along the scan-chain. When a bit position reaches the input of an EXOR gate connecting two scan-chain segments, it is used to pass either the serial Scan_In value or its complement downstream. This way the same Scan_In value is passed in true or complemented form at multiple bit positions (i.e. at each EXOR position) including the serial input to the scan-chain. This creates the opportunity to us a single Scan_In value to create different values at multiple positions of the scan-chain if one can control (or have knowledge of) the given values of the scan-chain bits that are also connected to the EXOR gates. This way it may be possible first to fill some of the non-Care_In positions with certain bit values so that when these values reach the inputs to the EXOR gates, the Scan_In input can be used to fill multiple bit positions with selected values. Since the number of Care_In positions is a small percentage of the total number of bits along the scan-chain, there are many non-Care_In positions that can be used in this fashion. This increases flexibility and makes it more likely that shorter-length Scan_In sequences can be found to fill all of the Care_In bit positions with pre-determined values while other bits may be filled with supporting values. [0040] The present invention is aimed at determining the best supporting values for the non-Care_In bit positions so that the minimum number of scan cycles is sufficient to set all of the Care_In positions to their targeted values. FIG. 5a shows a 10-bit scan chain broken into 4 segments of 3, 2, 2, and 3 bits, respectively. As an example, assume that the initial state of the scan-chain is 100,01,10,000 and the target values are 1d1,0d,d1,01d, where “d” represents a don't care value for a non-Care_In bit position. The response of the scan-chain to the serial Scan_In sequence of 10110 is displayed in FIGS. 5b through 5f. It is seen that starting with the present state of 100,01,10,000, serial input sequence of 10110 brings the scan-chain to the final state of 101,00,11,010 which satisfies the requirement that the Care_In positions are set to their target values of 1d1,0d,d1,01d. In other words, given the 10-bit scan-chain with a starting state of 100,01,10,000 it takes only 5 scan cycles to set all of the Care_In bit positions to their target values. Since the total shift count is less than the length of the scan-chain this represents an accelerated scan operation whereby 5 scan cycles have been sufficient to achieve the results to be expected after 10 scan cycles using traditional scan. Therefore, the scan architecture described above has been termed accelerated scan. [0041] Accelerated scan is based on the two separate technique namely the technique for reducing Scan_Out cycles using a checksum or MISR and the technique for opportunistic scan that uses existing values in the scan-chain to load the Care_In values with new values. Using a MISR for reducing Scan_Out cycles has been suggested also by others in the literature, but identifying Care_Out bit positions, and performing Scan_Out operations to the extent that Care_Out bit values (i.e. not the entire scan-chain) have been observed is novel and is a key feature of the present invention. This way, the number of cycles needed for observing the test results are reduced from “L”, where “L” is the total length of the scan-chain, to the minimum number of scan out operations necessary to capture only the Care_Out bit values, which is likely to be different for each different test vector. Opportunistic Scan is a novel technique that takes advantage of existing values in the scan-chain in order to set the Care_In values to pre-determined values using less than “L” cycles for the scan-in operations. Like traditional scan, accelerated scan uses overlapped scan-in and scan-out operations for consecutive test vectors by choosing the length of each scan cycle to be the longer of the scan-in and scan-out cycles that are being overlapped. This way, accelerated scan achieves loading the Care_In bits with their targeted values within the minimum number of shift cycles which is the lower of [0042] A—minimum number of shift cycles to scan out the contents of all Care_Out bits into a MISR (or checksum), and [0043] B—minimum number of shift cycles to set all of the Care_In bits with their desired values using opportunistic scan. [0044] Accelerated scan is applied to each scan test vector individually and uses the present values in the scan-chain to load the Care_In bits with their target values. In a preferred embodiment, the present state of the scan-chain represents the test results captured by the application of the previous test vector. The present values in the entire scan-chain may be used to load the target values into the Care_In bits, but it is also necessary to scan out the present values of the Care_Out bits since only these bits carry useful information regarding the pass/fail status of the previous test that was applied. Test results can be captured into a MISR (or checksum), which has taps from multiple bit positions along the scan-chain. Typically, the tap positions are fixed (by the designer) but each result vector may have Care_Out bits in different positions along the scan-chain. The value of each Care_Out bit is captured in the MISR (or checksum) by shifting it into a bit position from which a tap is taken into the MISR (or checksum). Hence, all Care_Out bit positions are captured (i.e. observed) after at least “T” shift cycles where “T” is the maximum distance (in number of bit positions) from any Care_Out bit position to the first MISR (or checksum) tap position that is ahead of it (i.e. closer to the Scan_Out port). Thus, for each new previous-result/current-test scan vector pair there is a minimum number of shift cycles that is necessary in order to capture all Care_Out values from the previous-result vector. Therefore, it is possible to focus on using opportunistic scan to load the Care_In values, as described above, but the resulting Scan_In vector may need to be rejected and a longer one may need to be found if it is shorter than the minimum shift-count “T” that is necessary to read out all of the Care_Out values. [0045] Formulation of the basic problem statement for using accelerated scan method is: [0046] Given the starting state of the scan-chain and the positions and the desired values of the Care_In values, determine the shortest scan sequence in order to set the Care_In bits with pre-determined values such that the shift count is not less than the minimum number of Scan_Out cycles required to capture all of the Care_Out values in the MISR (or checksum). [0047] This problem can be solved as follows: [0048] The present state of the scan chain is given as:S=Sn, {Sn-1, Sn-2, Sn-3, . . . S0}[0049] Where, [0050] Si={0, 1, U (unknown)} and Sn represents the serial Scan_In value while {Sn-1, Sn-2, Sn-3, . . . S0} represents the present contents of the scan-chain. [0051] Let C={Cn-1, Cn-2, Cn-3, . . . C0} be a set of constants, each corresponding to an element of S, such that Ci=0 if Si+1 feeds data directly into Si, and Ci=1, if EXOR(Sn, Si-1) feeds data into Si. The next state, S+, of the scan-chain can be expressed such that each bit of S+ is of the form: Si+=EXOR (Si-1, Ci & Sn) [0052] where “&” represents the logic AND function. [0053] Using the above given formulation and the starting scan-chain values that are expressed as logic 0, 1 or U, symbolic simulation can be used to compute new values at each bit position after each shift cycle. Each Scan_In value is represented by a new symbol at the Scan_In port such that as new symbols become entered into the scan-chain through the Scan_In port, they affect values in some of the bit positions, either directly (as in bit position “n”) or through an EXOR gate. The following table shows the values that would be computed using symbolic simulation for the output of each EXOR gate:
1Si-1SnCiSi+= EXOR(Si-1, Ci & Sn)U?0Uregular shift with an unknown (“X”) valueD?0Dregular shift with D value?U1UEXOR with an unknown inputU?1UEXOR with an unknown inputD01Dregular EXOR operationD11-Dregular EXOR operation0D1Dregular EXOR operation1D1-Dregular EXOR operationDaDb1DcDc = Da (+) Db
[0054] where “U”, D or Di (i=a, b, c, . . . ) represent any value or symbol except an unknown (U) value or symbol, and “-D” represents the inverse (i.e. NOT) of D. Symbol “(+)” is used to indicate the EXCLUSIVE-OR (i.e. EXOR) function. Furthermore, “?” represents any known value. [0055] Using the above formulation, expressions for each bit position of the scan-chain can be expressed and evaluated after each shift cycle by performing symbolic computation. A valid solution is indicated if the resulting evaluation shows no conflicts of the scan-chain contents with the desired Care_In values. If the present shift cycle does not represent a valid solution then a new cycle of shift must be simulated and the evaluations are repeated. In addition, if a conflict-free solution is found but the number of shift cycles needed to reach that solution is less than the minimum number of shift cycles needed to capture all of the Care_Out values from the previous-result vector, then the solution is rejected and at least one more shift cycle is evaluated for a new solution. The property of completeness of accelerated scan assures that eventually a solution will be found and further that this solution will require at most as many shift cycles as there are individual bits along the scan chain. [0056] Applying this procedure to the example shown above produces the results shown in FIG. 6a through FIG. 6e. FIG. 6a shows the starting state of the scan-chain and shows its next state after 1 shift cycle while a symbolic value of “A” is applied at the Scan_In port. FIGS. 6b through 6e show the state of the scan-chain after each shift cycle. FIG. 6c shows that at the 3rd shift cycle it becomes necessary to enter a new variable, “Z” into the scan chain and record the relationship that “Z=C (+) A” as an EXOR equation that needs to be satisfied. After each shift cycle, it is checked to see if the symbolic values that are present in the scan-chain can be assigned to satisfy the Care_In values as well as allowing all of the EXOR equations to be solved without any conflicts. For the example, given the Care_In values of 1d1, 0d, d, 1, 01d, the first solution is found after the 5th shift cycle by setting E=1, C=1, S=0, W=1, U=0, and using these values to solve for the remaining variables and EXOR equations as Z=1, Y=0, T=1, A=0, B=1, D=0, and E=1. Thus, the final desired Scan_In sequence, which is given by ABCDE=01101. This sets the final state of the scan-chain as 101, 00, 11, 010 that satisfies the requirement that the Care_In values should be set to 1d1,0d,d1,01d. [0057] This example demonstrates that setting the symbolic values so that A=0, B=1, C=1, D=0, E=1 satisfies the conditions represented by the EXOR equations as well as achieving the desired values in the Care_In positions. Therefore, the 5-bit serial input sequence of E, D, C, B, A=1, 0, 1, 1, 0 (value for A is fed into the scan-chain first) achieves the Care_In values in the 10-bit long scan-chain. [0058] A software program can be developed that implements the procedure described above for finding the shortest Scan_In sequence to set all Care_In values to the desired values. As the length of the scan chain grows and the scan chain is broken into more segments, ver}