这个配置玩lol可以吗-学路网-学习路上 有我相伴
这个配置玩lol可以吗
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网友碰到这么一个问题:这个配置玩lol可以吗,具体如下:这配置玩lol高配可以吗？系统通过互联网整理（主要来自百度知道、sogou问问、知乎、360问答等平台）获得以下解决方法，供碰到同样问题的网友参考:解决方法1：妥妥的最高画质没问题，GTX1080TI的显卡，带吃鸡都没毛病，i7 8700K这款CPU，很流畅，16G的RAM，开游戏之后大约占25%。望采纳。解决方法2：可以玩的， 英雄联盟的配置要求不高如果您还有更好的解决方法也可以告诉我们啊，添加我们统一服务微信公众号：vcshuo
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联想台式机安装拯救系统3.0安装过程有图
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本帖最后由 dqlfx 于
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　　我的电脑是2008年购买的联想KX8020，随机系统为WINDOWSVISTA，去年安装WINDOWS7.0后，WINDOWS下无法安装一键恢复5.3，只能在开机时通过按隹“LVT”键的方法进入一键拯救系统2.0，只有一个“恢复出厂设置”。如果安装一键恢复7.0不能使用，后来安装联想台式机安装拯救系统3.0成功。具体方法和步骤如下：
　　1.准备Win7_Product_Recovery_Boot_Disc_PE_V1_3_iso 光盘，如果没有可下载南狮王KINGLION　WIN7PE　RTM3.0.090727。本人认为只要是WINPE3.0均可以使用。
　　2.准备Recovery Disc PE For Tinian3.0 DVD1(SC) V1.0.iso光盘。
　　3.准备disc pe for ideacdntre kx v5.0光盘，如果有联想分区隐藏工具，可不用此光盘。
　　备份硬盘上所有文件！！将硬盘重新分区，分两个分区，C盘分区格式化，第二个分区最好大于30G不要格式化，准备做隐藏分区使用。
1.放入南狮王KINGLION　WIN7PE　RTM3.0.090727，设置为光盘启动，进入WINPE3.0
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2.点击“安装程序”
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3.完成后自动退出安装程序，取出光盘，放入Recovery Disc PE For Tinian3.0 DVD1(SC) V1.0.iso , 点击“我的电脑”，
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4.打开“CD驱动器”，
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5.点击“APPS.BAT”
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6.输入1，回车
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7.这时，安装程序会退出，重复4.5.6步骤，我本人认为这是安装程序重新分配盘符导致CD驱动器的盘符改变所致。最后进入如下界面
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8.输入1，回车
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9.输入5，回车，实际选择哪个选项由你自己决定，本人计划安装WIN7.0　32位操作系统，所以选择此项。
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10.出现如下界面输入1，回车
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11.下面选择安装语言，选择b是简体中文，不要选错！！
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12.回车，开始安装，记住不管何时安装程序自动退出，只要重复以上步骤即可。
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13.看仔细了，最后出现如下界面时，程序即将安装完成，
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程序安装完成后自动退出。至此，联想拯救系统安装完成，取出Recovery Disc PE For Tinian3.0 DVD1(SC) V1.0.iso光盘，
放入disc pe for ideacdntre kx v5.0光盘，如果有联想分区隐藏工具，可不用此光盘。
下一步将最后一个分区的FAT分区记录创建到MBR,隐藏最后一个分区：
(末完待续）
1.重启电脑，选择第3个选项，回车。
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2.输入dir,打开文件列表
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3.输入hdtool.exe&&/mbr,回车
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4.输入hdtool.exe /hid,回车
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5.完成后，看一下隐藏分区是否正常，输入hpatool.exe /view，回车
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6.如上图，是否为“YES”，按住电源键关机。重新启动机器，
在有自检有LENOVO画面时，按键盘上的LVT键或F2键，出现如下界面证明安装正确，退出,安装操作系统。
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操作系统安装完成后，重新启动，进入联想拯救系统3.0点击“驱动与软件安装”完成驱动和随机软件的安装。
将系统和软件更新为最新，重新启动，进入联想拯救系统3.0点击“一键恢复”可将当前系统备份为出厂设置。
如果有了联想售后服务光盘2.0，安装步骤就会很简单：
1、准备联想售后服务光盘[url=]Product.Recovery.Dics.For.WIN7.0.2.0.iso[/url]
2、准备Win7_Product_Recovery_Boot_Disc_PE_V1_3_iso 光盘
3、联想最新驱动光盘：联想电脑驱动程序V6.9A，现在最新版本应该比这个更高
安装步骤：
A、放入1光盘，屏幕提示需放入光盘时，放入2光盘
B、放入2光盘，光盘自动运行，自动制作隐藏分区，一路出现提示放入驱动光盘3
C、放入光盘3，自动复制光盘驱动和安装程序到隐藏分区，完成后，提示取出光盘
D、按任意键关机
E、重启放入系统安装光盘安装操作系统
D、安装完成操作系统，重启电脑进入一键恢复，点击安装驱动软件，会重启进入WINDOWS安装电脑驱动和随机软件
E、重启电脑进入一键恢复，备份操作系统
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怎么没有看到图啊？？？？
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请问版主我怎么能删除最后一个图片“剪贴板10.jpg“？？？？
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支持楼主经验共享！！！不错！！
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怎么没看到要放出驱动光盘这个图片我安装时也没放入驱动光盘这项
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怎么没看到要放出驱动光盘这个图片我安装时也没放入驱动光盘这项
苍龙九啸 发表于
& & 我的就有这个选项啊？？？？怎么会没有啊？？？
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顶了，弄了半天，我差两步。谢谢楼主！:D
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怎么没看到要放出驱动光盘这个图片我安装时也没放入驱动光盘这项
苍龙九啸 发表于
& & 他不是用Product_Recovery_Boot_Disc_PE_V2.0引导盘安装的,就不会出现放驱动盘这项.
1.用引导盘安装,就不用准备disc pe for ideacdntre kx v5.0光盘.
2.用引导盘安装,分区结构有变化,到最后只剩下隐藏分区了,其它为末分配,需要重新分区.
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目前只发现按照官方提供的安装方法进行安装的.
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他不是用Product_Recovery_Boot_Disc_PE_V2.0引导盘安装的,就不会出现放驱动盘这项.
weiwei1234 发表于
& & 嗯我没用引导盘安装用的OKR7.0引导到PEDOS下的,没用引导盘安装在分区上会出现三个分区中间有一个9GB的空间
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嗯我没用引导盘安装用的OKR7.0引导到PEDOS下的,没用引导盘安装在分区上会出现三个分区中间有一个 ...
苍龙九啸 发表于
7.JPG (56.8 KB, 下载次数: 1)
09:17 上传
只要出现放入驱动光盘安装
Insert the next Application DVD into the optical drive.
Press 'Y' key to continue, press 'N' key to skIp.
选'N&,然后放入驱动光盘,回车.出现下面的
Rescue System restore completed.
Press any key to reboot and install OS or other operation.
Take out Driver CD or DVD
&&任意键后,自动启动电脑.
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如果出现几个G的末分配空间，可在WINDOWS下打开“控制面板-管理工具-计算机管理-磁盘管理”对末分配空间进行分配。这个分区是创建隐藏分区时从最后一个分区分出来的。好像隐藏分区默认为25.1G。
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请楼主提供Recovery Disc PE For Tinian3.0 DVD1(SC) V1.0.iso
disc pe for ideacdntre kx v5.0的下载地址
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支持楼主经验共享！！！不错！！
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多出来的9.8G的分区&&只要记录了引导信息：执行hdtool /mbr ——&hdtool /hid& & 完后&&装系统时可删掉&&本人使用的是1.3版本的
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只要出现放入驱动光盘安装
Insert the next Application DVD into the optical ...
weiwei1234 发表于
为什么我的是Insert the next Application DVD into the optical drive.
Press any key to continue
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12345678PCB STACK UPLAYER 1 : TOP LAYER 2 : GND LAYER 3 : IN1ACW3 BLOCK DIAGRAMCLOCK GENERATORLAYER 4 : IN3 LAYER 5 : VCC LAYER 6 : IN2 LAYER 7 : GND LAYER 8 : BOT FSB 533/667MHZPG.37AYonah/Merom(478 Micro-FCPGA)PG.3PG. 4,5 NVIDIA G72M-V + 2 PIECES OF VRAM 64M/128M PG.14,15,16,17 LVDSCharger--MAX8724DDRII-SODIMM1DDR2 (MAX8632)PG.38BDDRII 533/667MHZPCI-EPG.12,13NORTH BRIDGE Calistoga GM/PMDDRII 533/667MHZLVDS (LCD CONN)PG.22BDDRII-SODIMM2VCCP(MAX8743)PG.391466 BGA VGA PG.6,7,8,9,10,11 DMI Interface USB2.0 USB2.0 USB2.0PG.12,13CRTPG.23BluetoothPG.31CPU Power MAX8771PG.40SATA - HDDD/D (MAX8734)PG.41SATAUSB2.0 Port 0 ~ 3PG.28PG.24ICH7-MPCI-ELAN88E6 PG.29 RJ45/RJ11 PG.30Discharge CircuitPG.42CODD(CD-ROM)PG.24IDE652 BGAPCI-EMINI PCI-E SocketPG.35 PCI BUS 33MHzCVGA (MAX1993)PG.43Azalia PG.18,19,20,21CARDBUS PC7412Conexant Audio CX20551-22 PG.32 PCMCIA CON. PG.26 Card Reader PG.27 IEEE1394 CONN. PG.25 LPC PG.25,26,27AUDIO Amplifier PG.33MDC DAA CX20548 PG.34KBCNS87541V PG.36 X-BusSuper IOLPC47N217DDInternal Speaker & Mic PG.33Audio Jacks PG.33Keyboard con. PG.31Touch Pad PG.318M Flash PG.36IrDA PG.35 PG.35PROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberBlock DiagramWednesday, March 29, 20067Rev 3A 18Sheetof4312345654321Board Stack up DescriptionPCB LayersLayer Layer Layer Layer Layer Layer Layer Layer 1 2 3 4 5 6 7 8TOP GND IN1 IN3 SVCC IN2 GND BOTTOMVoltage RailsVoltage RailsVCC_CORE +1.5V +1.05V 5V_S5/3V_S5/1.5V_S5 5VSUS/3VSUS/1.8VSUS SMDDR_VTERM/+2.5VRUN/+3VRUN/+5VRUN/+12VRUN +VCC_GFX_CORE/+1.2V_GFX_PCIE LANVCC 3VPCU 5VPCUON S0~S2 ON S3X X X X X X X X X X X XON S4ON S5Control signalVRON MAINON MAINONDDXXS5_ON SUSON MAINON MAINON LAN_ON VL VLX X XX X XX X XPower On Sequencing Timing Diagram VID VRON VCC_CORECTsft_star_vcc Vboot Tboot Tboot-vid-tr Tcpu_upCVidCPU_UP Vccp Vccp_UP Vccgmch GMCHPWRGD CLK_ENABLE# IMVP4_PWRGDTvccp_upACINTgmch_pwrgd ACIN 5VPCU/3VPCU Tcpu_pwrgd NBSWON#POWER ON TIMINGPCI DEVICE PCI7412 IDSEL# AD25 REQ# / GNT# REQ0# / GNT0# Interrupts INT B#/C#/D#DNBSWON#To ICH7YONAH Power-up Timing SpecificationsS5_ON To ICH7TdRSMRST# SUSB#,SUSC# From ICH7BRESET#BSUSONFrom 97551 From 97551 From 97551BCLKMAINONTcVSUS,VCCTePWRGOODTa Tb TfVRON 1.5V/1.05V VCC_COREVCC VID[5:0]Vcc,bootCLK_EN#To clock generatorPWROK PLTRST#\PCIRST#99ms & t 214To GMCH/other PCI deviceAVCCPTa=VCC and VCCP asseration to VID[5:0] vaild Tb=VID[5:0] stable to VCC vaild Tc=BCLK stable to PWRGOOD assertion Td=PWRGOOD to RESET# de-assertion time Te=Vcc,boot vaild to PWRGOOD assertion timeAPROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberSYSTEM INFORMATIONWednesday, March 29, 20061Rev 3ASheet2of43543212345678FSC FSB FSA 1 0 0 0ACPU 100 133 166 200 266 333 400 RSVDSRC 100 100 100 100 100 100 100 100PCI 33 33 33 33 33 33 33 33C246 33P 2 1 VR_PWRGD_CK410# PM_STPPCI# PM_STPCPU# 2 C233 33P 2 1 1 Y1 U14 14.318MHZ XOUT 50 49 10 55 54 XTAL_IN XTAL_OUT Vtt_PwrGd#/PD PCI/SRC_STOP# CPU_STOP# VDDA_CR XIN0 0 1 1 0 0 1 11 1 1 0 0 0 0 1Place these termination to close CK410M. Cause those Pin-out is for Current-Mode.R198 1 R203 1 R189 1 R193 1 37 38 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/FA0 1 1 1GNDAVDDAREF0 CPU0 CPU0# CPU1 CPU1#52 44 43 41 40 36 35 33 32 31 30 26 27 24 25 22 23 19 20 17 18 5 4 3 56 9 814M_REF R_HCLK_CPU R_HCLK_CPU# R_HCLK_MCH R_HCLK_MCH# R_PCIE_NEW R_PCIE_NEW# R_PCIE_MINI R_PCIE_MINI# R_MCH_3GPLL R_MCH_3GPLL# R_PCIE_SATA R_PCIE_SATA# R_PCIE_LAN R_PCIE_LAN# R_PCIE_ICH R_PCIE_ICH# R_PCIE_VGA R_PCIE_VGA# R_DREFSSCLK R_DREFSSCLK# R_PCLK_SIO R_PCLK_PCM R_PCLK_LPC_DEBUG R_PCLK_LPC R_PCLK_ICH PCIF0 4 2 4 2 2 4 2 4 2 4 2 4 2 4 R175 R170 R171 R173 R185 1 1 1 1 1 4 2 4 2 T270 T271 3 RP11 1 4P2R-S-33 3 RP13 1 4P2R-S-33 PAD PAD CLK_PCIE_MINI 3 RP17 CLK_PCIE_MINI# 1 4P2R-S-33 CLK_MCH_3GPLL 3 RP18 CLK_MCH_3GPLL# 1 4P2R-S-33 CLK_PCIE_SATA 1 RP19 CLK_PCIE_SATA# 3 4P2R-S-33 CLK_PCIE_LAN 1 RP20 CLK_PCIE_LAN# 3 4P2R-S-33 CLK_PCIE_ICH 1 RP21 CLK_PCIE_ICH# 3 4P2R-S-33 CLK_PCIE_VGA RP15 1 CLK_PCIE_VGA# 3 4P2R-S-33 DREFSSCLK 1 RP14 DREFSSCLK# 3 4P2R-S-33 PCLK_541 2 33 PCLK_PCM 2 33 2 33 PCLK_LPC_DEBUG PCLK_LPC 2 33 PCLK_ICH 33 2 2 *10K 2 10K 2 *10K 2 10K +3VRUNR168 1 CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 633 2 114M_ICH2020,40 VR_PWRGD_CK410# 20 PM_STPPCI# 20 PM_STPCPU#CPU2_ITP/SRC7 CPU2#_ITP/SRC7#SMbus address D227 20 TI_CLK48M CLKUSB_48CGCLK_SMB CGDAT_SMB TI_CLK48M CLKUSB_48R199 1 R206 1 R167 1 C223 12 10 2 10 2 3346 47 CLK_BSEL0 CLK_BSEL1 CLK_BSEL2 VDDREF_CR CLKVDD CLKVDD1 CLKVDD 12 16 53 48 42 1 7 21 28 34 11 IREF 39SCLK SDATACK-410MSRC6 SRC6# SRC5 SRC5# SRC4_SATA SRC4#_SATA SRC3 SRC3# SRC2 SRC2# SRC1 SRC1#CLK_PCIE_MINI 35 CLK_PCIE_MINI# 35 CLK_PCIE_3GPLL 8 CLK_PCIE_3GPLL# 8 CLK_PCIE_SATA 18 CLK_PCIE_SATA# 18 CLK_PCIE_LAN 29 CLK_PCIE_LAN# 29 CLK_PCIE_ICH 19 CLK_PCIE_ICH# 19 CLK_PCIE_VGA 14 CLK_PCIE_VGA# 14 DREFSSCLK 8 DREFSSCLK# 8 PCLK_541 36 PCLK_PCM 25 PCLK_LPC_DEBUG 35 PCLK_LPC 35 PCLK_ICH 19B35 14M_SUPERIO +3VRUN L25 1 2 SBK1Y-N 0.047U 1 1 C299 C283 0.047U 1 C302 C306 1 CLKVDD C310FSA/USB_48MHz FSB/TEST_MODE FSC/REF1 VDD_REF VDD_CPU VDD_PCI_1 VDD_PCI_2 VDD_SRC0 VDD_SRC1 VDD_SRC2 VDD_48 IREF*10P 2120 ohms@100MhzB212220.047U R209 1 2.2 20.047U4.7U VDD48_CR VDDA_CR 1 C293 1 C297 4.7U 8 8 DOT96 DOT96#2Iref=5mA, Ioh=4*IrefDOT96 DOT96# 4P2R-S-33 4 2 RP121 R2072 475/FSRC0/DREFSSCLK SRC0#/DREFSSCLK# PCI5 PCI4 PCI3 PCI2 PCIF1/100_96M# PCIF0/ITP_EN0.047U 23 R_DOT96 1 R_DOT96#14 15DOT96MHz DOT96MHz#GND_48 GND_REF GND_PCI_1 GND_PCI_2 GND_SRC GND_CPU213 51 2 6 29 45ICS954206AG-T1 R181 1 R182 1 R177 1 R178250mA ( MAX. ) +3VRUNDREFSSCLK Frequency Select. &0& : 96MHz &1& : 100MHzTie to VCC (Logic 1) is for ITP using. Tie to GND (Logic 0) is for PCIE using.(PIN 35,36)C111PCLK_PCM PCLK_ICH PCLK_541 PCLK_LPCL20 +3VRUN 2 1 SBK1Y-N C239 0.047U C240 0.047U 2 C245 4.7U 2 CLKVDD1 CLK_PCIE_LAN CLK_PCIE_LAN# CLK_PCIE_MINI CLK_PCIE_MINI# R246 1 R245 1 R225 1 R228 1 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F 2 49.9/F2C222 *10PC120 ohms@100Mhz+1.05VR115 R110 R1111K 0 1KR116 R1032.2K 1KCLK_BSEL0 C238 MCH_BSEL0 8 *10P C248 *10P C263 *10P C315 *10PCLK_MCH_3GPLL R230 1 CLK_MCH_3GPLL# R234 1 CLK_PCIE_SATA CLK_PCIE_SATA# R244 1 R243 1 R248 1 R247 1 R205 1 R208 1 R196 1 R201 1 R210 1 R215 14 CPU_BSEL0R192 12 2.2 2 1 C278VDD48_CR C274 4.7U 2 CLK_PCIE_ICH CLK_PCIE_ICH# DREFSSCLK DREFSSCLK# DOT96 DOT96# 10.047U +3VRUN +1.05V R131 R124 R125 1K 0 *0 Q21 20DR132 R1170 1KCLK_BSEL1 R186 1 1R 2 1 2 4 VDDREF_CR C257 0.047U24 CPU_BSEL1MCH_BSEL1 8 2RP10 4P2R-S-10KCLK_PCIE_VGA CLK_PCIE_VGA#PDAT_SMBPDAT_SMB3 CH2507SPT +3VRUN1CGDAT_SMBCGDAT_SMB 12,35Stuff 0 ohm for 533MHz, NC for 667MHz+1.05V R151 R145 R146 1K 0 *0 R152 R138 4.7K 1K CLK_BSEL2 Q20 4 CPU_BSEL2 MCH_BSEL2 8 20 PCLK_SMB PCLK_SMB 3Place these termination to close CK410M. Cause those Pin-out is for Current-Mode.1 32D21 CH2507SPTCGCLK_SMBCGCLK_SMB 12,35 Size Date: Document NumberPROJECT : CW3 Quanta Computer Inc.CLOCK GENERATORWednesday, March 29, 20067Rev 3A 43Sheet38of12345654321T10 6 H_A#[31:3] U26A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 K3 H2 K2 J3 L5 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 A6 A5 C4 H_STPCLK_R# D5 C6 B4 A3 TP_A32# TP_A33# TP_A34# TP_A35# TP_A36# TP_A37# TP_A38# TP_A39# TP_APM0# TP_APM1# TP_HFPLL AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 B25 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01]# RSVD[02]# RSVD[03]# RSVD[04]# RSVD[05]# RSVD[06]# RSVD[07]# RSVD[08]# RSVD[09]# RSVD[10]# RSVD[11]# PZ-01 ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# PROCHOT THERMDA THERMDC THERMTRIP# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 H_RS#0 H_RS#1 H_RS#2PAD 6 6 6 +1.05V +1.05V +1.05V 3,5,6,8,9,10,18,21,39,42H_ADS# H_BNR# H_BPRI#CONTROLH_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6ADDR GROUP 0R69 56/FNear to MCH &500mils6 H_INIT# 18 H_LOCK# 6 H_CPURST# 6H_D#[63:0] U26B H_D#0 E22 H_D#1 F24 H_D#2 E26 H_D#3 H22 H_D#4 F23 H_D#5 G25 H_D#6 E25 H_D#7 E23 H_D#8 K24 H_D#9 G24 H_D#10 J24 H_D#11 J23 H_D#12 H26 H_D#13 F26 H_D#14 K22 H_D#15 H25 H23 G22 J26 H_D#16 N22 H_D#17 K25 H_D#18 P26 H_D#19 R23 H_D#20 L25 H_D#21 L22 H_D#22 L23 H_D#23 M23 H_D#24 P25 H_D#25 P22 H_D#26 P23 H_D#27 T24 H_D#28 R24 H_D#29 L26 H_D#30 T25 H_D#31 N24 M24 N25 M26 AD26 R439 *1K/F 51 C26 D25 B22 B23 C21 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10 D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2] PZ-01 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# AA23 H_D#32 AB24 H_D#33 V24 H_D#34 V26 H_D#35 W25 H_D#36 U23 H_D#37 U25 H_D#38 U22 H_D#39 AB25 H_D#40 W22 H_D#41 Y23 H_D#42 AA26 H_D#43 Y26 H_D#44 Y22 H_D#45 AC26 H_D#46 AA24 H_D#47 W24 Y25 V23 AC22 H_D#48 AC23 H_D#49 AB22 H_D#50 AA21 H_D#51 AB21 H_D#52 AC25 H_D#53 AD20 H_D#54 AE22 H_D#55 AF23 H_D#56 AD24 H_D#57 AE21 H_D#58 AD21 H_D#59 AE25 H_D#60 AF25 H_D#61 AF22 H_D#62 AF26 H_D#63 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6 COMP0 COMP1 COMP2 COMP3 27.4/F 54.9/F 27.4/F 54.9/FH_D#[63:0] 6DD6 6H_ADSTB#0 H_REQ#[4:0]H_RS#[2:0] 6 H_TRDY# 6 H_HIT# H_HITM# 6 6T13PAD6H_A#[31:3]XDP/ITP SIGNALSAD4 T18 PAD AD3 T2 PAD AD1 T145 PAD AC4 T3 PAD AC2 AC1 XDP_BPM#5 XDP_TCK AC5 T6 PAD XDP_TDI AA6 XDP_TDO AB3 XDP_TMS AB5 XDP_TRST# AB6 C20 XDP_DBRESET# SYS_RST# 20 D21 A24 A25 C7 T183 H_PROCHOT# THERMDA THERMDC PM_THRMTRIP# 8,18 PAD CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 PAD T41 T14 T16 T11 T138 T17 T42 T40 T188 PADXDP PU_R & 0.2&XDP_BPM#4 +1.05V 6 6 6 6 T4 PADH_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[63:0]DATA GRP 2DATA GRP 0H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6R80 75/F18 18 18 18CH_A20M# H_FERR# H_IGNNE# R32 0 H_INTR H_NMI H_SMI#DATA GRP 36H_ADSTB#1DATA GRP 1THERMH_STPCLK# 18 18 18 PAD PAD PAD PAD PAD PAD PAD PAD PAD PADH CLKTrcae width : ? placement &0.5&CBCLK[0] BCLK[1] RSVD[12]#A22 A21 T180 T22 TP_EXTBREF D2 F6 D3 C1 AF1 D22 C23 C24 TP_SPARE0 TP_SPARE1 TP_SPARE2 TP_SPARE3 TP_SPARE4 TP_SPARE5 TP_SPARE6 TP_SPARE7+1.05VT15 T7 T5 T9 T143 T142 T141 T140 T139 T1225/25mils H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 R95 R94 R30 R29RESERVEDR92 1K/F PAD PAD PAD PAD PAD PAD PAD PAD R93 2K/FPAD T186RSVD[13]# RSVD[14]# RSVD[15]# RSVD[16]# RSVD[17]# RSVD[18]# RSVD[19]# RSVD[20]#6 6 6H_DSTBN#1 H_DSTBP#1 H_DINV#1+1.05VH_GTLREFMISC20/15mils R438T187 PADR31 *200/FICH_DPRSTP# 18,40 H_DPSLP# 18 H_DPWR# 6 H_PWRGD 18 H_CPUSLP# 6,18 PSI# 40 H_PWRGD is CMOS driving by ICH+1.05V 5VSUS3 3 3CPU_BSEL0 CPU_BSEL1 CPU_BSEL2TO VRDBXDP_TCK PD 27.4/1% ? XDP_TRST PD 510ohm /5% ? XDP_TDI PU 150ohm /1.05V XDP_TMS PU 39.2/1%? XDP_TDO PU 54.9ohm? For ITP700XDP_TMS XDP_TDI XDP_BPM#5R23 R28 R2454.9/F 54.9/F 54.9/F 2 *54.9/F *0.1U H_PROCHOT# R425 10K R99 *330 +3VRUN +3VRUNBXDP_DBRESET# R75 C660XDP_TCK XDP_TRST#R22 R2554.9/F 54.9/FQ17 *PDTC144EU231VR_TT# 40Q28 3 MB_DATA CH2507SPT MB_DATA 36,371+3VRUN +3VRUN R407 R409 15 15 THDAT_SMB THCLK_SMB U28 THERMDC 1 3 2 4 VCC DXN DXP -OVT SMDATA SMCLK -ALT GND 7 KBSMDAT 8 KBSMCLK 6 5+3VRUN15 MIL200/F 3V_THM C521 R408 0 0.1U R426 0210KQ27 3 MB_CLK CH2507SPT MB_CLK 36,371*010 mil trace / 10 mil spaceTHERMDA +3VRUNAC522 2200P12 R429THRM#20MAX6657ADDRESS:98HR430 10KA+3VRUN 2 3 *CH2507SPT Q29 1411999_SHDN#PROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberYONAH CPU (1 of 2)Wednesday, March 29, 2006 Sheet1Rev 3A of 434543254321VCC_CORE U26C A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[68] VCC[002] VCC[69] VCC[003] VCC[70] VCC[004] VCC[71] VCC[005] VCC[72] VCC[006] VCC[73] VCC[007] VCC[74] VCC[008] VCC[75] VCC[009] VCC[76] VCC[010] VCC[77] VCC[011] VCC[78] VCC[012] VCC[79] VCC[013] VCC[80] VCC[014] VCC[81] VCC[015] VCC[82] VCC[016] VCC[83] VCC[017] VCC[84] VCC[018] VCC[85] VCC[019] VCC[86] VCC[020] VCC[87] VCC[021] VCC[88] VCC[022] VCC[89] VCC[023] VCC[90] VCC[024] VCC[91] VCC[025] VCC[92] VCC[026] VCC[93] VCC[027] VCC[94] VCC[028] VCC[95] VCC[029] VCC[96] VCC[030] VCC[97] VCC[031] VCC[98] VCC[032] VCC[99] VCC[033] VCC[100] VCC[034] VCC[035] VCCP[01] VCC[036] VCCP[02] VCC[037] VCCP[03] VCC[038] VCCP[04] VCC[039] VCCP[05] VCC[040] VCCP[06] VCC[041] VCCP[07] VCC[042] VCCP[08] VCC[043] VCCP[09] VCC[044] VCCP[10] VCC[045] VCCP[11] VCC[046] VCCP[12] VCC[047] VCCP[13] VCC[048] VCCP[14] VCC[049] VCCP[15] VCC[050] VCCP[16] VCC[051] VCC[052] VCCA VCC[053] VCC[054] VCC[055] VID[0] VCC[056] VID[1] VCC[057] VID[2] VCC[058] VID[3] VCC[059] VID[4] VCC[060] VID[5] VCC[061] VID[6] VCC[062] VCC[063] VCC[064] VCC[065] VCCSENSE VCC[066] VCC[067] VSSSENSE PZ-01 AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 AD6 AF5 AE5 AF4 AE3 AF2 AE2VCC_CORE +1.05V VCC_CORE +1.5V +1.05V 3,4,6,8,9,10,18,21,39,42 VCC_CORE 40,42 +1.5V 8,9,10,19,21,35,39,42U26D A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24DDVCC_COREC84 10UC504 10UC513 10UC511 10UC505 10UC72 10UC514 10UC63 10UCC148 10UC131 10UC509 10UC170 10UC+1.05VC516 10UC93 10UC121 10UC98 10UC495 330U/2.5V/ESR-9/POS +ESR :12m ohm+1.5VC175 10UC118 10UC508 10UC53 10UC536 0.01UC538 10UC138 10UC39 10UC141 10UC172 10U+ C652 220U/4V/25m+1.5VBC515 10UC510 10UC151 10UC85 10UBC81 10UC164 10UC33 10UC68 10UH_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID640 40 40 40 40 40 40VCC_CORER42 100/F VCCSENSE 40 VSSSENSE 40AF7 AE7R38 100/F VCC_CORE +1.05VAAC162 10UC146 10UC503 10UC31 10UC157 0.1UC73 0.1UC159 0.1UC74 0.1UC17 0.1UC18 0.1UPZ-01PROJECT : CW3 Quanta Computer Inc.Size Date:5 4 3 2Document NumberYONAH CPU (2 of 2)Wednesday, March 29, 2006 Sheet1Rev 3A of 43554321H_XRCOMP R123 24.9/F4H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING T81 PAD PAD F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 E1 E2 E4 Y1 U1 W1 AG2 AG1U30A H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN# H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_HIT# H_HITM# H_LOCK# H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13 J7 W8 U3 AB10 K4 T7 Y5 AC4 K3 T6 AA5 AC5 D3 D4 B3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31H_A#[31:3] 4 +1.05V +1.05V 3,4,5,8,9,10,18,21,39,4215 mils/10milsDD+1.05VR137 54.9/F H_XSCOMP+1.05VR102 221/F H_XSWING+1.05VCR104 100/FC197 0.1UH_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4 H_DBSY# 4 H_DEFER# 4 H_DPWR# 4 H_DRDY# 4 H_DINV#[3:0] 4 C218 0.1U H_DSTBN#[3:0] 4R164 100/F H_VREF C220 0.1U R163 200/FCHOSTR4430+1.05VH_VREFR172 54.9/F H_YSCOMPH_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3+1.05VH_DSTBP#[3:0] 4BBR176 221/F H_YSWINGR180 100/FC258 0.1UH_HIT# 4 H_HITM# 4 H_LOCK# 4 H_REQ#[4:0] 4H_YRCOMP R187 24.9/FH_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY#D8 G8 B8 F8 A8 B4 E6 D6 E3 E7H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2H_RS#[2:0] 43 CLK_MCH_BCLK 3 CLK_MCH_BCLK#T8215 mils/10milsAShort Stub & 100mils extract from same pointH_CPUSLP# 4,18 H_TRDY# 4ACalistogaPROJECT : CW3 Quanta Computer Inc.Size Date:5 4 3 2Document NumberGMCH HOST (1 of 6)Wednesday, March 29, 2006 Sheet1Rev 3A 436of5432112DM_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3U30E SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 Calistoga SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 AU23 AK16 AK18 AR27 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 TP_MB_RCVENIN# TP_MB_RCVENOUT# M_B_BS#0 12,13 M_B_BS#1 12,13 M_B_BS#2 12,13 M_B_CAS# 12,13 M_B_DM[7:0] 12D12M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8U30D SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 Calistoga SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 AW14 AK23 AK24 AY14 M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 TP_MA_RCVENIN# TP_MA_RCVENOUT# M_A_BS#0 12,13 M_A_BS#1 12,13 M_A_BS#2 12,13 M_A_CAS# 12,13 M_A_DM[7:0] 12M_B_DQS[7:0] 12B MEMORYCM_A_DQS[7:0] 12SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#M_B_DQS#[7:0] 12CAM_B_A[13:0] 12,13MEMORYM_A_DQS#[7:0] 12M_A_A[13:0] 12,13SYSTEMDDRSYSTEMBM_B_RAS# 12,13 T77 PAD T78 PAD M_B_WE# 12,13BDDRT75 T76M_A_RAS# 12,13 PAD PAD M_A_WE# 12,13AAPROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberGMCH DDR (2 of 6)Wednesday, March 29, 2006 Sheet1Rev 3A of 437543254321U30B PAD T65 PAD T72 PAD T71 PAD T193 PAD T196 PAD T74 PAD T73 PAD T63 PAD T68 PAD T69 PAD T66 PAD T202 PAD T192 PAD T201 PAD T48 PAD T200 3 MCH_BSEL0 3 MCH_BSEL1 3 MCH_BSEL2 PAD T44 PAD T54 PAD T43 PAD T49 CLK_MCH_OE# MCH_RSVD_1 MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8 TV_DCONSEL0 TV_DCONSEL1 MCH_RSVD_11 MCH_RSVD_12 MCH_RSVD_13 MCH_RSVD_14 MCH_RSVD_15 H32 T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41 A35 A34 D28 D27 K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26 G28 F25 H26 G6 AH33 AH34 H28 H27 K28 RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN# SDVO_CTRLCLK SDVO_CTRLDATA LT_RESET# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 Calistoga SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP# SM_RCOMP SM_VREF_0 SM_VREF_1 G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41 AF33 AG33 A27 A26 C40 D41 AE35 DMI_TXN0 AF39 DMI_TXN1 AG35 DMI_TXN2 AH39 DMI_TXN3 AC35 AE39 AF35 AG39 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 M_RCOMP# M_RCOMP M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_OCDCOMP_0 M_OCDCOMP_1 M_ODT0 M_ODT1 M_ODT2 M_ODT3 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13SMDDR_VREF_MCH 12 12 12 12 12 12 12 12R2260 1.8VSUSSMDDR_VREFR219 C304 R217 *10K/F 2 0.1U 1 *10K/F945GM/PMU30C R136 R149 L_CLKCTLA L_CLKCTLB R108 R107 L_IBG L_VBG R130 *0 *0 *0 *0 *0 D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37 L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK# LA_CLK LB_CLK# LB_CLK EXP_A_COMPI EXP_A_COMPO EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_1520mils/20mils space+V1.5_PCIE D40 EXP_A_COMPX D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40 R121 24.9/FRSVD15,22 LCD_CTL 15,22 LCD_BLON PADT62 PADT61 15,22 EDIDCLK 15,22 EDIDDATA PAD T57 15,22 DISP_ON L_IBG PAD T195 PAD T47 R118 1.5K/FDMUXING15mils/15milsLA_CLK# LA_CLK LB_CLK# LB_CLK LA_DATAN0 LA_DATAN1 LA_DATAN29 MCH_CFG_13 PAD T45 PAD T70 PAD T67CLKMCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 MCH_CFG_19 MCH_CFG_20LA_DATA#_0 LA_DATA#_1 LA_DATA#_2PCIE_MRX_GTX_N0 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N7 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N15 PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P15 PCIE_MTX_GRX_N0_C PCIE_MTX_GRX_N1_C PCIE_MTX_GRX_N2_C PCIE_MTX_GRX_N3_C PCIE_MTX_GRX_N4_C PCIE_MTX_GRX_N5_C PCIE_MTX_GRX_N6_C PCIE_MTX_GRX_N7_C PCIE_MTX_GRX_N8_C PCIE_MTX_GRX_N9_C PCIE_MTX_GRX_N10_C PCIE_MTX_GRX_N11_C PCIE_MTX_GRX_N12_C PCIE_MTX_GRX_N13_C PCIE_MTX_GRX_N14_C PCIE_MTX_GRX_N15_C PCIE_MTX_GRX_P0_C PCIE_MTX_GRX_P1_C PCIE_MTX_GRX_P2_C PCIE_MTX_GRX_P3_C PCIE_MTX_GRX_P4_C PCIE_MTX_GRX_P5_C PCIE_MTX_GRX_P6_C PCIE_MTX_GRX_P7_C PCIE_MTX_GRX_P8_C PCIE_MTX_GRX_P9_C PCIE_MTX_GRX_P10_C PCIE_MTX_GRX_P11_C PCIE_MTX_GRX_P12_C PCIE_MTX_GRX_P13_C PCIE_MTX_GRX_P14_C PCIE_MTX_GRX_P15_C 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C210 C545 C214 C547 C219 C550 C225 C553 C237 C555 C253 C557 C262 C559 C279 C561 C208 C544 C212 C546 C217 C549 C221 C551 C234 C554 C247 C556 C256 C558 C271 C560 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15DLVDSDDRLA_DATAP0 LA_DATAP1 LA_DATAP2 Layout as short as passable NC from WW45 PADT60 PADT52 PADT59 LB_DATAN0 LB_DATAN1 LB_DATAN2B37 B34 A36 G30 D30 F29LA_DATA_0 LA_DATA_1 LA_DATA_2 LB_DATA#_0 LB_DATA#_1 LB_DATA#_2SMDDR_VREF_MCHCPCI-EXPRESS20 PM_BMBUSY# 12 PM_EXTTS#0 20 PM_EXTTS#1 4,18 PM_THRMTRIP# 20,40 DELAY_VR_PWRGOOD 19 PLT_RST-R# R322 RST IN# MCH 100/F PAD T64 PAD T46 R109 T194 T205 T190 T209 T207 T208 T88 T87 T86 T204 T198 T83 T84 T206 T80 T203 T199 T197 T191 *10K/FCLK_PCIE_3GPLL# 3 CLK_PCIE_3GPLL 3 DOT96# 3 DOT96 3 DREFSSCLK# 3 DREFSSCLK 3 DMI_TXN[3:0] 19 +1.5VPADT56 PADT50 PADT58LB_DATAP0 LB_DATAP1 LB_DATAP2F30 D29 F28LB_DATA_0 LB_DATA_1 LB_DATA_2GRAPHICSR197 *40.2/FR218 *40.2/FCFG PMMISCCR445 R446 R447 R150 R444 DMI_TXP[3:0] 19 DMI_RXN[3:0] 190 TV_COMP_C 0 TV_Y/G_C 0 TV_C/R_C 0 TVIREF 0 TV_IRTNA16 C18 A19 J20 B16 B18 B19TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNCTV+3VRUN 19 MCH_ICH_SYNC PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PADBTP_MCH_NC0 D1 TP_MCH_NC1 C41 TP_MCH_NC2 C1 TP_MCH_NC3 BA41 TP_MCH_NC4 BA40 TP_MCH_NC5 BA39 TP_MCH_NC6 BA3 TP_MCH_NC7 BA2 TP_MCH_NC8 BA1 TP_MCH_NC9 B41 TP_MCH_NC10 B2 TP_MCH_NC11 AY41 TP_MCH_NC12 AY1 TP_MCH_NC13 AW41 TP_MCH_NC14 AW1 TP_MCH_NC15 A40 TP_MCH_NC16 A4 TP_MCH_NC17 A39 TP_MCH_NC18 A3AE37 DMI_RXN0 AF41 DMI_RXN1 AG37DMI_RXN2 AH41DMI_RXN3 AC37 DMI_RXP0 AE41 DMI_RXP1 AF37 DMI_RXP2 AG41 DMI_RXP3DMINC15,23 15,23 15,23CRT_B CRT_G CRT_RR433 R434 R435*0 *0 *0CRT_BLUE CRT_GREEN CRT_RED CRT_COM#E23 D23 C22 B22 A21 B21 C26 C25 G23 J22 H23CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNCVGA23 CRT_DDCCLK 23 CRT_DDCDAT DMI_RXP[3:0] 19 15,23 CRT_HSYNCR105 R106*0 *0R144 R162 R143*39/FHSYNC1B& 0.1& . 15mils/15mils space use 1% R1.8VSUS +3VRUN 15,23 CRT_VSYNC*255/F CRTIREF *39/F VSYNC1 CalistogaPCIE_MTX_GRX_P[0..15] 14 PCIE_MTX_GRX_N[0..15] 14 10K/F *10K/F PM_EXTTS#0 PM_EXTTS#1 15,22 TXLCLKOUT15,22 TXLCLKOUT+ 15,22 15,22 15,22 15,22 15,22 15,22 TXLOUT0TXLOUT0+ TXLOUT1TXLOUT1+ TXLOUT2TXLOUT2+ RP7 3 1 RP6 1 3 RP9 1 3 RP8 1 3 *0X2 4 2 *0X2 2 4 *0X2 2 4 *0X2 2 4 LA_CLK# LA_CLK LA_DATAN0 LA_DATAP0 LA_DATAN1 LA_DATAP1 +1.05V LA_DATAN2 LA_DATAP2 CRTIREF CRT_COM# CRT_BLUE CRT_GREEN CRT_RED R161 R98 R442 R440 R441 R449 R450 R451 R101 R148 R142 0 0 0 0 0 *150/F *150/F *150/F *0 0 0 L_CLKCTLA L_CLKCTLB R160 R159 10K/F 10K/F +3VRUN PCIE_MRX_GTX_P[0..15] 14 PCIE_MRX_GTX_N[0..15] 14R127 R232 80.6/F R156 M_RCOMP#15mils/10milsM_RCOMP MCH_CFG_9 R112 R233 80.6/F *10K/F +3VRUN945GM/PMAA+V1.5_PCIE +3VRUN SMDDR_VREF 1.8VSUS+V1.5_PCIE 10 +3VRUN 3,4,9,10,12,14,15,16,18,19,20,21,22,24,28,31,32,35,36,38,42,43 SMDDR_VREF 12,38 1.8VSUS 9,12,38,42,43HSYNC1 VSYNC1945GM/PM9 MCH_CFG_[20:3]MCH_CFG_[20:3] Size Date: Document NumberPROJECT : CW3 Quanta Computer Inc.GMCH DMI VEDIO (3 of 6)Wednesday, March 29, 20061Rev 3ASheet8of43543254321U30G +1.05V + C543 330U/2.5V/ESR-9/POS AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16 VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 +1.05V C203 AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 330U/2.5V/ESR-9/POSU30F VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U1725milsVCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107 C309 0.47U AU41 AT41 VCC_SM1 C301 0.47U AM41VCC_SM2 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 + PC54 BA30 330U C295 AY30 AW30 10U AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 C651 + AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 C291 AY22 0.47U AW22 AV22 AU22 place C49 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 C322 AW15 0.47U AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 25mils AL6 AK6 AJ6 0.47U AV1 VCC_SM106 C308 AJ1 VCC_SM107 C292 0.47U 330U/2.5V/ESR-9/POS+C270 10UC267 10UC227 1UC273 0.1UC231 0.1UC224 0.1U1.8VSUS120milsDDC296 10UC307 0.47UC317 0.1UC318 0.1UC319 0.1U+1.5V VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57 AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15100milsCCC321 0.47Uplace C50 on BA23 BallNCTFon AJ23 Ball3,4,5,6,8,10,18,21,39,42+1.05V+1.05V 1.8VSUS8,12,38,42,43 1.8VSUSVCCBBGMCH Strap pin8 MCH_CFG_5 8 MCH_CFG_6 8 MCH_CFG_7 8 MCH_CFG_9 8 MCH_CFG_10 8 MCH_CFG_11 8 MCH_CFG_12 8 MCH_CFG_13 8 MCH_CFG_16 8 MCH_CFG_18 8 MCH_CFG_19 8 MCH_CFG_203Calistoga *2.2K 1.MCH_CFG_5 Low = DMI X2, High=DMIX4 *2.2K *2.2K 4.MCH_CFG_9 PCI Exp Graphics Lane: Low =Reserved,High=Mobility *2.2K *2.2K 7.MCH_CFG_16 FSB Dynmic ODT: Low=Dynamic ODT Disabled, High=Dynamic ODT Enabled. *2.2K 8.MCH_CFG_18 VCC Select: LOW=1.05V, High=1.5V *2.2K *2.2K *2.2K R166 CFG_RSVD_0_R *1K/F *1K/F *1K/F *0 +3VRUN 9.MCH_CFG_19 DMI LANE Reversal:Low=Normal,High=LANES Reversed. 10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only SDVO or PCIE x1 is operational (defaults) ,High=SDVO and PCIE x1 are operation simultaneously via the PEG port. 5.MCH_CFG_10 Host PLL VCC Select: Low=Reserved, High=Mobility 6.MCH_CFG_11: Low=Calistoga, High=Reserved 2.MCH_CFG_6 DDR : Low =Moby Dick, High= Calistoga (Default) 3.MCH_CFG_7 CPU Strap Low=RSVD, High=Mobile CPUR114 R126 R120 R139 R129 R113 R153 R165 R140 R155 R158 R157AA+3VRUN Size +3VRUN Date:2PROJECT : CW3 Quanta Computer Inc.Document NumberCalistoga5 425milsGMCH Pw & Strap(4 of 6)Wednesday, March 29, 2006 Sheet1Rev 3A9of4354321+1.5V L4310uH+V3.3_TVDAC 80mils +V1.5_DPLLA L16 *FCM +V3.3_ATVBG C182 + C528 330U C537 0.1U +V1.5_DPLLB 10U C533 0.1U C190 0.022U+2.5VRUN +V3.3_ATVBG R91 0 R431 0 +V1.5_PCIE +2.5VRUN +1.5V R427 *0+1.05V C541 0.1U C187 10U U30H VCC_SYNC H22 C30 B30 A30 AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 F21 E21 G21 B26 C39 AF1 VCC_LCD_1 A38 B39 AF2 H20 G20 +V3.3_ATVBG VCCSYNC VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS VCCA_MPLL VCCA_TVBG VSSA_TVBG VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76 +1.05V AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1 330U/2.5V/ESR-9/POS+V3.3_ATVBG L44D+ C202C269 4.7UC229 2.2UC232 0.1UC268 10U10uH+V3.3_ATVBG C535 0.1U + C525 330U C540 0.1U +V1.5_HPLL +V3.3_ATVBG C534 0.1U C287 10U C288 0.1U +V1.5_MPLL +V3.3_ATVBG +2.5VRUN C275 10U C280 0.1U R428 *0 R432 0 +V3.3_ATVBG C542 0.01U C539 0.1U C191 0.022U +V3.3_ATVBG +V2.5_CRTDAC C192 0.022U +V3.3_ATVBG +V1.5_3GPLL C186 0.1UD+1.05VC567 0.1UC568 10UL23FCMC226 0.22UC228 0.22UC230 0.47UC272 0.47UC185 0.1UC189 0.022U+V1.5_DPLLA +V1.5_DPLLB +V1.5_HPLLL22FCM+2.5VRUN+V1.5_MPLLC204 0.1UC178 4.7U+2.5VRUN R119 10C25milsVCCGFOLLOWD3 PDZ5.6B 1 2+1.05V C532 0.1U +1.05V R89 +V3.3_ATVBG 0 +1.5V +1.5V R448 R436 +3VRUN +1.5V *0 0 +V1.5_TVDAC +3VRUN C194 10U C198 0.1U C294 0.1U C266 10U 40mils +V1.5_QTVDAC +1.5V C216 0.022U E19 F19 C20 D20 E20 F20 AH1 AH2 VCC_LCD_2 A28 B28 C28 D21 A23 B23 B25 H19 AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCD_TVDAC VCC_HV0 VCC_HV1 VCC_HV2 VCCD_QTVDAC VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40 CalistogaL15 *FCM+V2.5_CRTDAC+V3.3_ATVBGCPOWER+V1.5_PCIE L19 100nH60milsR100 0 PCIE_L+1.5VC566 10UC563 10U+ C565 330URC0805+V1.5_3GPLL R460 0.5/F60mils 60milsL45 1uH 3GPLL_FB_R 3GPLL_FB_L R459 0+1.5VC195 0.47UBRC080560mils+V1.5_TVDAC L18 V15_TVDAC_R R97 0 +1.5VBDELR457, C290FCM C205 0.022U +V1.5_QTVDAC +1.5V L17 C206 0.1URC0805C196 C2760.22U 0.47U30milsV1_5SFOLLOW R90 +3VRUN 10 R96AD2 1 PDZ5.6BFCM C215 0.022U C209 0.1U+V3.3_TVDACRC08050A+1.05V +1.5V +V1.5_PCIE +2.5VRUN +3VRUN+1.05V 3,4,5,6,8,9,18,21,39,42 +1.5V 5,8,9,19,21,35,39,42 +V1.5_PCIE 8 +2.5VRUN 15,23,42 +3VRUN 3,4,8,9,12,14,15,16,18,19,20,21,22,24,28,31,32,35,36,38,42,43PROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberGMCH Power 2 (5 of 6)Wednesday, March 29, 2006 Sheet1Rev 3A 4310of543254321U30I AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 Calistoga VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11U30J VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 Calistoga VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1DDVSSVSSCCBBAAPROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberGMCH GND (6 of 6)Wednesday, March 29, 2006 Sheet1Rev 3A of 4311543212345678+3VRUN 1.8VSUS+3VRUN 1.8VSUSA3,4,8,9,10,14,15,16,18,19,20,21,22,24,28,31,32,35,36,38,42,43 8,9,38,42,43 SMDDR_VREF_DIMM 1.8VSUS 1.8VSUS CN19 1 VREF VSS46 2 M_A_DQ4 3 VSS47 DQ4 4 M_A_DQ1 M_A_DQ0 5 DQ0 DQ5 6 M_A_DQ5 7 DQ1 VSS15 8 M_A_DM0 9 VSS37 DM0 10 M_A_DQS#0 11 DQS#0 VSS5 12 M_A_DQ7 M_A_DQS0 13 DQS0 DQ6 14 M_A_DQ6 15 VSS48 DQ7 16 M_A_DQ2 17 DQ2 VSS16 18 M_A_DQ3 M_A_DQ13 19 DQ3 20 DQ12 M_A_DQ14 21 VSS38 DQ13 22 M_A_DQ12 23 DQ8 VSS17 24 M_A_DQ8 M_A_DM1 25 DQ9 DM1 26 27 VSS49 VSS53 28 M_CLK_DDR0 M_A_DQS#1 29 DQS#1 CK0 30 M_CLK_DDR#0 M_A_DQS1 31 DQS1 CK0# 32 33 VSS39 VSS41 34 M_A_DQ9 M_A_DQ10 35 DQ10 DQ14 36 M_A_DQ15 M_A_DQ11 37 DQ11 DQ15 38 39 VSS50 VSS54 40 M_A_DQ16 M_A_DQ17 M_A_DQS#2 M_A_DQS2 M_A_DQ23 M_A_DQ19 M_A_DQ24 M_A_DQ25 M_A_DM3 M_A_DQ26 M_A_DQ27 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) PAD1 DDR2_SODIMM VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 PAD2 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 M_A_DQ20 M_A_DQ21 PM_EXTTS#0 M_A_DM2 M_A_DQ18 M_A_DQ22 M_A_DQ29 M_A_DQ28 M_A_DQS#3 M_A_DQS3 M_A_DQ30 M_A_DQ31 M_CKE1M_A_DM[0..7] 7 M_A_DQ[0..63] 7 M_A_DQS[0..7] 7 M_A_DQS#[0..7] 7 M_A_A[0..13] 7,13SMDDR_VREF_DIMM SMDDR_VREF_DIMM 1.8VSUS CN20 M_B_DQ0 M_B_DQ5 M_B_DQS#0 M_B_DQS0 M_B_DQ7 M_B_DQ3 M_B_DQ9 M_B_DQ8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) PAD1 2- VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 PAD2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 M_B_DQ4 M_B_DQ1 M_B_DM0 M_B_DQ2 M_B_DQ6 M_B_DQ12 M_B_DQ13 M_B_DM1 M_CLK_DDR3 M_CLK_DDR#3 M_B_DQ14 M_B_DQ15 1.8VSUSM_B_DM[0..7] 7 M_B_DQ[0..63] 7 M_B_DQS[0..7] 7 M_B_DQS#[0..7] 7 M_B_A[0..13] 7,131.8VSUSPlace these Caps near So-Dimm1.C580 2.2UC577 2.2UC584 2.2U1.8VSUS Placethese Caps near So-Dimm1.AC576 0.1U M_CLK_DDR3 8 M_CLK_DDR#3 8C585 0.1UC581 0.1UC587 0.1UM_CLK_DDR0 8 M_CLK_DDR#0 8M_B_DQS#1 M_B_DQS1 M_B_DQ11 M_B_DQ10SMDDR_VREF_DIMM M_B_DQ16 M_B_DQ21 PM_EXTTS#0 M_B_DM2 M_B_DQ18 M_B_DQ22 M_B_DQ24 M_B_DQ25 M_B_DQS#3 M_B_DQS3 M_B_DQ26 M_B_DQ27 1.8VSUS M_CKE3 M_CKE3 8,13 PM_EXTTS#0 8 C392 0.1U C351 2.2U+3VRUNM_B_DQ20 M_B_DQ17 PM_EXTTS#0 8 M_B_DQS#2 M_B_DQS2 M_B_DQ19 M_B_DQ23 M_B_DQ29 M_B_DQ28 M_B_DM3 M_B_DQ31 M_B_DQ30 M_CKE1 8,13 8,13 7,13 M_CKE2 M_B_BS#2 M_CKE2 M_B_BS#2 M_B_A12 M_B_A9 M_B_A8 M_B_A5 M_B_A3 M_B_A1 M_A_BS#1 7,13 M_A_RAS# 7,13 M_CS#0 8,13 M_ODT0 8,13 M_B_A10 M_B_BS#0 M_B_WE# M_B_CAS# M_CS#3 M_ODT3 M_B_DQ37 M_B_DQ33 M_B_DQS#4 M_B_DQS4 M_B_DQ39 M_B_DQ35 M_B_DQ41 M_B_DQ40 M_B_DM5 M_B_DQ46 M_B_DQ43 M_B_DQ53 M_B_DQ49 M_CLK_DDR1 8 M_CLK_DDR#1 8PC4800 DDR2 SDRAM SO-DIMM (200P)C350 2.2UC373 0.1UPC4800 DDR2 SDRAM SO-DIMM (200P)Place these Caps near So-Dimm1. No Vias Between the Trace of PIN to CAP.B8,13 7,13M_CKE0 M_A_BS#2M_CKE0 M_A_BS#2 M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1 M_A_A10 M_A_BS#0 M_A_WE# M_A_CAS# M_CS#1 M_ODT1 M_A_DQ35 M_A_DQ37 M_A_DQS#4 M_A_DQS4 M_A_DQ38 M_A_DQ39Place these Caps near So-Dimm2.BM_A_A11 M_A_A7 M_A_A6 M_A_A4 M_A_A2 M_A_A0 M_A_BS#1 M_A_RAS# M_CS#0 M_ODT0 M_A_A13M_B_A11 M_B_A7 M_B_A6 M_B_A4 M_B_A2 M_B_A0 M_B_BS#1 M_B_RAS# M_CS#2 M_ODT2 M_B_A13 M_B_BS#1 7,13 M_B_RAS# 7,13 M_CS#2 8,13 M_ODT2 8,13C578 2.2UC582 2.2UC586 2.2U1.8VSUS Placethese Caps near So-Dimm1.7,13 7,13 7,13 8,13 8,13M_A_BS#0 M_A_WE# M_A_CAS# M_CS#1 M_ODT17,13 7,13 7,13 8,13 8,13M_B_BS#0 M_B_WE# M_B_CAS# M_CS#3 M_ODT3C579 0.1UC583 0.1UC589 0.1UC320 0.1UM_A_DQ32 M_A_DQ36 M_A_DM4 M_A_DQ33 M_A_DQ34 M_A_DQ44 M_A_DQ45 M_A_DQS#5 M_A_DQS5 M_A_DQ43 M_A_DQ47 M_A_DQ52 M_A_DQ53 M_CLK_DDR1 M_CLK_DDR#1 M_A_DM6 M_A_DQ54 M_A_DQ55 M_A_DQ61 M_A_DQ57 M_A_DQS#7 M_A_DQS7 M_A_DQ59 M_A_DQ63 R297 R296 10K 10K 3,35 CGDAT_SMB 3,35 CGCLK_SMB +3VRUNM_B_DQ32 M_B_DQ36 M_B_DM4 M_B_DQ34 M_B_DQ38 M_B_DQ44 M_B_DQ45 M_B_DQS#5 M_B_DQS5 M_B_DQ47 M_B_DQ42 M_B_DQ52 M_B_DQ48 M_CLK_DDR2 M_CLK_DDR#2 M_B_DM6 M_B_DQ55 M_B_DQ50 M_B_DQ56 M_B_DQ61 M_B_DQS#7 M_B_DQS7 M_B_DQ62 M_B_DQ63 R312 R309 +3VRUN 10K 10K R319 M_CLK_DDR2 8 M_CLK_DDR#2 8SMDDR_VREF_DIMM+3VRUNC414 0.1UC402 2.2UC400 2.2UC410 0.1UCCM_A_DQ40 M_A_DQ41 M_A_DM5 M_A_DQ42 M_A_DQ46 M_A_DQ48 M_A_DQ49Place these Caps near So-Dimm2. No Vias Between the Trace of PIN to CAP.M_A_DQS#6 M_A_DQS6 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ60 M_A_DM7 M_A_DQ62 M_A_DQ58 CGDAT_SMB CGCLK_SMB +3VRUNDM_B_DQS#6 M_B_DQS6 M_B_DQ51 M_B_DQ54 M_B_DQ60 M_B_DQ57 M_B_DM7 M_B_DQ58 M_B_DQ59 CGDAT_SMB CGCLK_SMBSMDDR_VREF_DIMM R314 *10K/F *10K/FR3200SMDDR_VREF1.8VSUSDCLOCK 0,1CKE 0,1SMbus address A0CLOCK 3,4CKE 2,3SMbus address A4PROJECT : CW3 Quanta Computer Inc.Size Date: Document NumberDDR SO-DIMM(200P)Wednesday, March 29, 20067Rev 3A 43Sheet128of12345612345678DDRII DUAL CHANNEL A,B.A ADDRII A CHANNELM_A_A[13..0] SMDDR_VTERM SMDDR_VTERM SMDDR_VTERM C391 0.1U C404 0.1U C407 0.1U C423 0.1U C419 0.1U C406 0.1U C420 0.1U C405 0.1U C421 0.1U C408 0.1U C422 0.1U C386 0.1U C387 0.1U C388 0.1U C389 0.1U C390 0.1U M_A_A[13..0] 7,12 SMDDR_VTERM 38,42 SMDDR_VTERMDDRII B CHANNELM_B_A[13..0] 1.8VSUS +3VRUN M_B_A[13..0] 7,12 1.8VSUS 8,9,12,38,42,43 +3VRUN 3,4,8,9,10,12,14,15,16,18,19,20,21,22,24,28,31,32,35,36,38,42,43C358 0.1UC354 0.1UC352 0.1UC355 0.1UC356 0.1UC424 0.1UC418 0.1UC403 0.1UC385 0.1UC357 0.1ULayout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERMB B8,12M_ODT0M_ODT0 M_A_A13 M_A_A7 M_A_A5 M_A_A3 M_A_A1 M_A_A11 M_CKE1 M_A_A10 M_A_BS#0 M_A_A8 M_A_A6 M_A_A2 M_A_A4 M_A_A0 M_A_BS#1 M_A_A12 M_A_A9 M_A_CAS# M_CS#1RP33 RP29 RP27 RP38 RP26 RP37 RP36 RP35 RP28 RP251 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 32 56X2 4 2 56X2 4 2 56X2 4 2 4 2 4 2 4 2 4 56X2 56X2 56X2 56X27,12M_B_BS#1M_B_A0 M_B_BS#1 M_B_A3 M_B_A1 M_B_A12 M_B_A5 M_B_A2 M_B_A4 M_B_A8 M_B_A9 M_B_A6 M_B_A11 M_CKE2 M_B_BS#2 M_CS#3 M_B_RAS# M_B_WE# M_B_CAS# M_B_A10 M_B_BS#0RP48 RP41 RP42 RP49 RP43 RP50 RP44 RP47 RP45 RP40SMDDR_VTERM1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 32 56X2 4 2 56X2 4 2 56X2 4 2 4 2 4 2 4 2 4 56X2 56X2 56X2 56X2SMDDR_VTERM8,12 7,12M_CKE1 M_A_BS#0SMDDR_VTE}