手机device’s 没有sysconfigg 如何查看

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eth0: unknown interface: No such device
作者:cloves & 来源:转载 &
摘要: 用ifconfigeth0up,提示一下错误信息:eth0:unknowninterface:Nosuchdevice解决方法:1、进入/etc/sysconfig/network-scripts/目录,查看ifcfg-eth0配置信息,发现正确无误。2、查看/etc/udev/rules.d/70-persistent-net.rules,将其的MAC信息与ifcfg-eth0进行对比,发现也没
用ifconfig eth0 up,提示一下错误信息:
eth0: unknown interface: No such device
解决方法:
1、进入/etc/sysconfig/network-scripts/目录,查看ifcfg-eth0配置信息,发现正确无误。2、查看/etc/udev/rules.d/70-persistent-net.rules,将其的MAC信息与ifcfg-eth0进行对比,发现也没有错3、用ifconfig -a,发现没有eth0的任何信息,却有eth1的信息,故可能系统没有识别到eth04、进入/etc/sysconfig/network-scripts/目录,执行以下命令:
cp ifcfg-eth0 ifcfg-eth0.bak mv ifcfg-eth0 ifcfg-eth1
cp ifcfg-eth0 ifcfg-eth0.bakmv ifcfg-eth0 ifcfg-eth1
5、然后通过查看/etc/udev/rules.d/70-persistent-net.rules中eth1的MAC信息,将其与ifcfg-eth1中的MAC信息一致。6、最后,重启网络:service network restart,问题解决。
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IT知识库 IT610.com , All Rights Reserved.Bus interface system with two separate data transfer interfaces
United States Patent 6941408
The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.
Inventors:
Solomon, Richard L. (Colorado Springs, CO, US)
Application Number:
Publication Date:
09/06/2005
Filing Date:
09/30/2002
Export Citation:
LSI Logic Corporation (Milpitas, CA, US)
Primary Class:
Other Classes:
International Classes:
G06F13/14; G06F13/40; (IPC1-7): G06F13/14
Field of Search:
710/58-61, 710/305-317, 710/36-39, 710/7, 710/110-112, 710/105-107, 710/27-28, 710/20-22
View Patent Images:
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US Patent References:
6820165Pannell710/3136631437Callison et al.Pontius et al.710/1076578096Steinmetz et al.6564271Micalizzi, Jr. et al.6490644Hyde, II et al.6449677Olarig et al.6442641Bury et al.710/305Pannell6279051Gates et al.710/206266778Bell6233628Salmonsen et al.6170030Bell6088740Ghaffari et al.6067071Kotha et al.6065083Garcia et al.710/3156061754Cepulis et al.5991843Porterfield et al.5905876Pawlowski et al.5875343Binford et al.5745732Cherukuri et al.5682509Kabenjian710/3125634033Stewart et al.711/114
Foreign References:
EP0486230Device controller with separate data and command paths.
Primary Examiner:
Myers, Paul R.
Assistant Examiner:
Phan, Raymond N.
Attorney, Agent or Firm:
Suiter West Swantz PC LLO
1. An interface system suitable for coupling a bus interface controller with a back-end device, comprising: a bus
and a back-end device coupled to the bus interface controller via an interface, the interface including a command queuing interface suitable for enqu a command completion interface suitable for reporting tr an inbound data transfer interface suitable for transferring data from the bus interface controller to the back- and an outbound data transfer interface suitable for transferring data from the back-end device to the bus interface controller, wherein the inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously, wherein inbound data transfer interface and the outbound data transfer interface operate independently.
2. The interface system as described in claim 1, wherein command and control information are suitable for being exchanged on at least one of the command queuing interface and command completion interface while data is exchanged on the data transfer interface.
3. The interface system as described in claim 1, wherein data for a transaction is suitable for being moved without respect to a current transaction being requested on a control bus.
4. The interface system as described in claim 1, wherein the back-end device enqueues a transaction on the command queuing interface, at least one transfer of data is accomplished corresponding to the transaction queued on the command queuing interface, and completion status of the transaction is reported on the command completion interface.
5. The interface system as described in claim 1, wherein a plurality of transactions are queued, the transaction are completed without regard to an order the transactions are queued.
6. The interface system as described in claim 1, wherein the bus interface controller conforms to at least one of a USB standard, SCSI standard, fiber standard and the back-end device conforms to at least one of a PCI standard and PCI-X standard.
7. The interface system as described in claim 1, wherein a plurality of data transfers on the data transfer interface are executed, the plurality of data transfers corresponding to a transaction queued on the command queuing interface.
8. A method of transferring data between a back-end device and a bus interface controller, comprising: enqueueing a first transaction on a comma transferring data corresponding to the first transaction on a data transfer interface including an inbound data transfer interface and an outbound data transfer interface while simultaneously transferring data corresponding to a second transaction on the data transfer interface, wherein the data from the bus interface controller to the back-end device is transferred on the inbound data transfer interface and the data from the back-end device to the bus interface controller is transferred on the inbound data transfer interface, wherein the inbound data transfer interface and the outbound data transfer interface o and receiving notification of completion of the first transfer of data corresponding to the transaction, the notification reported on a command completion interface.
9. The method as described in claim 8, wherein a plurality of transactions are queued, the transaction are completed without regard to an order the transactions are queued.
10. The method as described in claim 8, wherein command and control information are suitable for being exchanged on at least one of the command queuing interface and command completion interface while data is exchanged on the data transfer interface.
11. The method as described in claim 8, wherein data for a transaction is suitable for being moved without respect to a current transaction being requested on a control bus.
12. The method as described in claim 8, wherein a back-end device enqueues a transaction on the command queuing interface, at least one transfer of data is accomplished corresponding to the transaction queued on the command queuing interface, and completion status of the transaction is reported on the command completion interface.
13. An interface system suitable for coupling a first bus interface controller with a second bus interface controller, comprising: a first bus interface controller suitable for coupling to a back- and a second bus interface controller suitable for coupling to an internal bus of an information handling system, wherein the second bus interface controller is coupled to the first bus interface controller via an interface including a command queuing interface suitable for enqu a command completion interface suitable for reporting tr a data transfer interface including a separate inbound data transfer interface suitable for transferring data from the first bus interface controller to the back- and a separate outbound data transfer interface suitable for transferring data from the back-end device to the first bus interface controller, wherein the separate inbound data transfer interface and the separate outbound data transfer interface are suitable for transferring the data independently.
14. The interface system as described in claim 13, wherein the inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.
15. The interface system as described in claim 13, wherein command and control information are suitable for being exchanged on at least one of the command queuing interface and command completion interface while data is exchanged on the data transfer interface.
16. The interface system as described in claim 13, wherein data for a transaction is suitable for being moved without respect to a current transaction being requested on a control bus.
17. The interface system as described in claim 13, wherein the back-end device enqueues a transaction on the command queuing interface, at least one transfer of data is accomplished corresponding to the transaction queued on the command queuing interface, and completion status of the transaction is reported on the command completion interface.
18. The interface system as described in claim 13, wherein a plurality of transactions are queued, the transaction are completed without regard to an order the transactions are queued.
19. The interface system as described in claim 13, wherein the first bus interface controller conforms to at least one of a USB standard, SCSI standard, fiber standard and the second bus interface conforms to at least one of a PCI standard and PCI-X standard.
20. The interface system as described in claim 13, wherein a plurality of data transfers on the data transfer interface are executed, the plurality of data transfers corresponding to a transaction queued on the command queuing interface.
Description:
CROSS REFERENCE TO RELATED APPLICATIONThe present invention incorporates U.S. patent application Ser. No. 09/736,883, filed Dec. 14, 2000, titled “Interface for Bus Independent Core” by reference in its entirety.FIELD OF THE INVENTIONThe present invention generally relates to the field of bus controllers, and particularly to an interface for a bus independent core.BACKGROUND OF THE INVENTIONInformation handling systems, such as desktop computers, servers, network appliances, and the like, are driving the expansion of the modern economy. Because information handling systems are performance driven, system throughput is vital for differentiating products, such as products that exchange massive amounts of information, both internally and externally, with storage devices, network interface cards, and the like. Therefore, increases in the ability to transfer data both within the system itself and transfer data over a network may afford competitive advantages for systems able to provide these advances.Once such problem is the transfer of data within the information handling system itself. Due to rapid advancements in processor speed, storage device access times, network speed, and the like, the bandwidth available within the system has steadily eroded. Thus, advancements in the ability of a system to input and output data are at the cutting edge of information handling system development. However, development of faster bus standards has encountered some limitations, namely the dependency of the operations of internal buses to external buses. For example, bus interface controller cores often have internal interfaces, which are tightly tied to the external bus. The internal interfaces may require agents connecting to them to have knowledge of various external bus characteristics, such as disconnection points and byte alignment. Previously, changes in external bus interfaces have required redesign of numerous internal modules. Although attempts have been made at removing external bus dependence from internal interfaces, changes in external bus interfaces typically require redesign of numerous internal modules.Therefore, it would be desirable to provide an interface for a bus independent core.SUMMARY OF THE INVENTIONAccordingly, the present invention is directed to an interface for a bus independent core. In a first aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.In a second aspect of the present invention, a method for transferring data includes enqueueing a transaction on a command queuing interface, transferring data corresponding to the transaction on a data transfer interface while simultaneously transferring data corresponding to a second transaction on the data transfer interface, and receiving notification of completion of the transfer of data corresponding to the transaction, the notification reported on a command completion interface.In a third aspect of the present invention, an interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller suitable for coupling to a backend device and a second bus interface controller suitable for coupling to an internal bus of an information handling system. The second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes a separate inbound data transfer interface suitable for transferring data and a separate outbound data transfer interface suitable for transferring data.It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.BRIEF DESCRIPTION OF THE DRAWINGSThe numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:FIG. 1 is an illustration of an exemplary embodiment of the present invention wherein an interface system includes a command queuing interface, data transfer interface and a command FIG. 2 is an additional illustration of an exemplary embodiment of the present invention wherein a variety of bus interfaces supported by a triple bus interface of the presentFIG. 3 is an illustration depicting an exemplary embodiment of the present invention wherein a backend device utilizes an interface of t andFIG. 4 is a highly diagrammatic view of an exemplary embodiment of the present invention wherein an interface system includes a command queuing interface, data transfer interface having separate buses, and a command completion interface.DETAILED DESCRIPTION OF THE INVENTIONReference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.Referring generally now to FIGS. 1 through 4, exemplary embodiments of the present invention are shown. The present invention is shown in conjunction with a bus suitable for operation in a Peripheral Component Interconnect (PCI) and PCI-X architectures. Although, a bus suitable for operation in both conventional PCI and PCI-X modes is described, a wide variety of bus architectures are contemplated without departing from the spirit and scope of the present invention.Referring now to FIG. 1, an exemplary embodiment 100 of the present invention is shown wherein an interface system includes a command queuing interface, data transfer interface and a command completion interface. Typically, bus interface controllers, such as controller cores and the like, have internal interfaces which are tightly tied to an external bus. The internal interfaces may require agents connecting to them to have knowledge of various external bus characteristics, such as disconnection points and byte alignment. Thus, previously, changes in external bus interfaces have required redesign of numerous internal modules. A bus interface of the present invention provides a generic interface that would not require an extensive redesign of numerous internal modules when utilizing a different bus interface controller, thereby greatly increasing the flexibility of the bus interface system.For example, a bus interface system 100 may include a first bus interface controller, in this instance a PCI-X core 102 coupled to a second bus interface controller, in this instance a SCSI core 104, via an interface 106. The interface 106 includes a command queuing interface 108, a data transfer interface 110 and a command completion interface 112. The command queuing interface 108 enables backend master devices to enqueue transactions. The command completion interface 112 enables a core to report transaction completion. Each exchange on the command completion interface 112 corresponds to a command enqueued on the command queuing interface 108. The data transfer interface 110 may be utilized to move data into (inbound) or out of (outbound) a backend master's buffer. Multiple transfers on the data transfer interface 110 may reference a single transaction queued on the command queuing interface 108. Thus, the command queuing interface 108, command completion interface 112 and data transfer interface 110 provide a de-coupled control/data path architecture to a backend master device. Command and control information may be exchanged on the command queuing interface 108 and command completion interface 112 while data is exchanged on the data transfer interface 110. Therefore, data for a given transaction may be moved without respect to transactions being requested on the control bus.Referring now to FIG. 2, an exemplary embodiment of the present invention is shown wherein a variety of bus interfaces are supported by a triple bus interface of the present invention. A bus interface system 200 may include a first bus interface 202, such as to a PCI bus, PCI-X bus, and the like, and a variety of additional bus interfaces, such as a SCSI interface 204, fiber interface 206, or other interface 208 as contemplated by a person of ordinary skill in the art. An arbiter 210 is provided for arbitration of commands. For example, the arbiter 210 may resolve competing demands for the interface. This may be accomplished by intercepting the commands from the first bus interface 202 and the variety of other bus interfaces provided 204, 206 &208. Preferably, only commands are intercepted, since the other data, such as completion and data includes ID and tag data.An interface 212 is included between the arbiter 210 and the first bus interface 202. The interface 212 includes a command queuing interface 214, a data transfer interface 216 and a command completion interface 218. The command queuing interface 214 enables the variety of second interface controllers 204, 206 &208 to enqueue transactions. The command completion interface 218 enables cores to report transaction completion. Exchanges on the command completion interface 218 correspond to a command enqueued on the command queuing interface 214.The data transfer interface 216 may be utilized to move data into (inbound) or out of (outbound) a backend master's buffer. Multiple transfers on the data transfer interface 216 may reference a single transaction queued on the command queuing interface 214. Thus, the command queuing interface 214, command completion interface 218 and data transfer interface 216 provide a de-coupled control/data path architecture to a backend master device. Command and control information may be exchanged on the command queuing interface 214 and command completion interface 218 while data is exchanged on the data transfer interface 216. Therefore, data for a given transaction may be moved from the second bus interface controller 204, 206 &208 without respect to transactions being requested by any other controller 204, 206 &208.In this way, command queuing and completion are separate from each other and from the data transfer path. Multiple agents may be supported, as well as multiple commands per agent. Data transfers may occur in any order, and have no dependence on possible alignment requirements of the external bus. Commands may also complete in any order.Referring now to FIG. 3, an exemplary embodiment of the present invention is shown wherein a backend device utilizes an interface of the present invention. Commands shown in the Figure correspond to the exemplary commands shown in the following discussion. In this example, a backend queues up three commands, Q1 302, Q2 304, and Q3 306 with attribute tags T1 308, T2 310 and T3 312. Q1 302 generates one data transfer cycle, X1314 to move the data and one completion cycle C1316 to acknowledge completion of the tag and signal the backend to retire tag T1. Q2 304 generates three data transfer cycles, X2 318 reflects a retry on the PCI bus without any data being moved, X3 320 moves some of the data, X5 322 moves the remaining data, and one completion cycle, C2 324 to acknowledge completion of the tag and signal the backend to retire tag T2. Q3 306 generates two data transfer cycles, X4 326 moves some of the data, X6 328 moves the remaining data, and once done, a completion cycle, C3 330 acknowledges completion of the tag and signals the backend to retire tag T3.In this way, command queuing and completion are separate from each other and from the data transfer path. Multiple agents may be supported, as well as multiple commands per agent. As shown in FIG. 3, data transfers may occur in any order, and have no dependence on possible alignment requirement of the external bus. Commands may complete in any order. Addresses and counts may be to byte-resolution. Although the use of an interface with respect to a PCI bus has been discussed, it should be readily apparent to a person of ordinary skill in the art that a variety of bus architectures are contemplated by the present invention without departing from the spirit and scope thereof.The following discussion lists exemplary commands which may be utilized to perform functions utilizing the present invention, an example of which is shown in FIG. 3. Outbound (O) refers to transaction in which data flows from a backend device to the PCI bus, and inbound (I) refers to transaction in which data flows from the PCI bus to a backend device.Command Queuing InterfaceBackend master devices enqueue transactions on this interface. The core will execute one or more transfers on the data transfer interface for each transaction queued on this interface. When the transaction is complete, a single completion status will be reported on the command completion interface.CmdSysAddr[63:0]IAddress in system memory to/from whichthe current transaction is directed.CmdLocalAddr[31:0]IAddress in the backend device's buffer spaceto/from which the current transaction isdirected.CmdLength[23:0]ILength of the current transaction.CmdInboundIHigh for transactions moving data from the PCIbus to the backend device. Low for transactionsmoving data from the backend device to thePCI bus.CmdType[1:0]IIdentifies the address space for the currenttransaction: 00=Memory, 01=I/O, 10=Config,11=Split Completion.CmdFunctionId[2:0]IIdentifier which connects transaction to a set ofconfiguration space data.CmdBackendId[3:0]IFixed identifier which is unique to the currentbackend device. The core uses this to connecttransaction data transfers to thecorrect backend.CmdTag[4:0]IIdentified which is unique to the currenttransaction. Must not be reused by the backenduntil the transaction has been retired.CmdRequestIDriven by the backend to indicate that theabove signals are stable and represent a desiredtransaction.
Command Completion InterfaceThe core reports transaction completion on this interface. Each exchange on this bus corresponds to a command enqueued on the command queuing interface.CompletionFunctionId[2:0]OIdentifier corresponding to backend device thatrequested the transaction which is being retired.CompletionBackendId[3:0]OIdentifier corresponding to backend device thatrequested the transaction which is being retired.CompletionTab[4:0]OIdentifier reporting the CmdTag from the transactionwhich is being retired.CompletionStatus[1:0]OReports the state of the transaction which is beingretired: 00 - GOOD - transaction complete without error 01 - ERROR - a data error occurred but thetransfer continued
to completion 10 - FAULT - the transaction ended with a fatalerror 11 - ReservedCompletionRequestODriven by the core to indicate that the abovesignals reflect a transaction to be retired.CompletionAcceptIDriven by the backend to indicate that it hasretired the referenced transaction.
Data Transfer InterfaceThe core uses this bus to move data into (inbound) or out of (outbound) a backend master's buffer. Multiple transfers on this bus may reference a single transaction queued on the command queuing interface.XferLocalAddr[31:0]OAddress in the backend device's buffer space to/fromwhich the current data transfer is being directed.XferLocalBE[7:0]OActive-high byte enables for the XferData busses.XferOutboundData[63:0]IThe core captures data off this bus for transfers movingdata from the backend device to the PCI bus.(XferInbound is low).XferInboundData[63:0]OThe core presents data on this bus for transfers movingdata from the PCI bus to the backend device.(XferInbound is high).XferInboundOHigh for transfers moving data from the PCI bus to thebackend device. Low for transfers moving data from thebackend device to the PCI bus.XferFunctionId[2:0]OIdentifier corresponding to backend device that requestedthe transaction which generated the current transfer.XferBackendId[3:0]OIdentifier corresponding to backend device that requestedthe transaction which generated the current transfer.XferTag[4:0]OIdentifier reporting the CmdTag from the transactionwhich generated the current transfer.XferRequestODriven by the core to indicate that the above signalsreflect a data transfer in progress.XferAcceptIDriven by the backend to indicate that it is ready with/forthe data transfer indicated by the above signals.XferDoneODriven by the core to indicate that the current datatransfer is complete. NOTE: This signal alone DOESNOT indicate that the transaction should be retired.
A variety of data transfer interfaces are contemplated by the present invention. For example, a data transfer interface may include a single bi-directional interface as previously described. Additionally, the data transfer interface may be divided into two or more separate buses.Referring now to FIG. 4, an exemplary embodiment 400 of the present invention is shown wherein an interface system includes a command queuing interface, an inbound data transfer interface, an outbound data transfer interface and a command completion interface. As previously described, typically, bus interface controllers, such as controller cores and the like, have internal interfaces which are tightly tied to an external bus. A bus interface of the present invention provides a generic interface that would not require an extensive redesign of numerous internal modules when utilizing a different bus interface controller, thereby greatly increasing the flexibility of the bus interface system.For example, a bus interface system 400 may include a bus interface controller, such as a PCI-X core 402 coupled to a back-end master device 404, such as a SCSI device, via an interface 406. The interface 406 includes a command queuing interface 408, an inbound data transfer interface 410, an outbound data transfer interface 412, and a command completion interface 414. The command queuing interface 408 enables backend master devices to enqueue transactions. The command completion interface 414 enables a core to report transaction completion. Each exchange on the command completion interface 414 corresponds to a command enqueued on the command queuing interface 408.In this instance, a data transfer interface is provided which has two independent buses, an inbound data transfer interface 410 and an outbound data transfer interface 412 which are utilized to move data into (inbound) or out of (outbound) a backend master's buffer, respectively. Outbound refers to transactions in which data flows from a backend device to a bus, such as a PCI bus. Inbound refers to transactions in which data flows from the PCI bus to the backend device. The present embodiment provides the ability to process inbound and outbound commands simultaneously, such as reads and writes. Thus, a core may pipeline data for an outbound transaction when an inbound transaction is received without contention for a single shared bus. Additional embodiments are contemplated in which dual-simplex bus interfaces are supported.As before, multiple transfers on the data transfer interface may reference a single transaction queued on the command queuing interface 408. Thus, the command queuing interface 408, command completion interface 414 and data transfer interface 410 &412 provide a de-coupled control/data path architecture to a backend master device. Thus, command and control information may be exchanged on the command queuing interface 408 and command completion interface 414 while data is exchanged on the inbound and outbound data transfer interfaces 410 &412. Therefore, data for a given transaction may be moved without respect to transactions being requested on the control bus.The core uses the data transfer interface to move data into (inbound) or out of (outbound) a backend master's buffer. Multiple transfers on the bus may reference a single transaction queued on the command queueing interface.XferInboundLocalAddr[31:0]OAddress in the backend device's buffer space towhich the current inbound data transfer is beingdirected.XferInboundLocalBE[7:0]OActive-high byte enables for the XferInboundDatabus.XferInboundData[63:0]OThe core presents data on this bus for transfersmoving data from the PCI bus to the backenddevice.XferInboundFunctionId[2:0]OIdentifier corresponding to backend device thatrequested the transaction which generated thecurrent inbound transfer.XferInboundBackendId[3:0]OIdentifier corresponding to backend device thatrequested the transaction which generated thecurrent inbound transfer.XferInboundTag[4:0]OIdentifier reporting the CmdTag from thetransaction which generated the current inboundtransfer.XferInboundRequestODriven by the core to indicate that the abovesignals reflect an inbound data transfer inprogress.XferInboundAcceptIDriven by the backend to indicate that it is readyfor the inbound data transfer indicated by theabove signals.XferInboundDoneODriven by the core to indicate that the currentinbound data transfer is complete. NOTE: Thissignal alone does NOT indicate that thetransaction should be retired.XferOutboundLocalAddr[31:0]OAddress in the backend device's buffer spacefrom which the current outbound data transfer isbeing directed.XferOutboundLocalBE[7:0]OActive-high byte enables for theXferOutboundData bus.XferOutboundData[63:0]IThe core captures data off this bus for transfersmoving data from the backend device to the PCIbus.XferOutboundFunctionId[2:0]OIdentifier corresponding to backend device thatrequested the transaction which generated thecurrent outbound transfer.XferOutboundBackendId[3:0]OIdentifier corresponding to backend device thatrequested the transaction which generated thecurrent outbound transfer.XferOutboundTag[4:0]OIdentifier reporting the CmdTag from thetransaction which generated the current outboundtransfer.XferOutboundRequestODriven by the core to indicate that the abovesignals reflect an outbound data transfer inprogress.XferOutboundAcceptIDriven by the backend to indicate that it is readywith the outbound data transfer indicated by theabove signals.XferOutboundDoneODriven by the core to indicate that the currentoutbound data transfer is complete. NOTE: Thissignal alone does NOT indicate that thetransaction should be retired.
It is believed that the interface of the present invention and many of its attendant advantages will be understood by the forgoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an explanatory embodiment thereof. It is the intention of the following claims to encompass and include such changes.
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