54321ShenZhen Topstar Industry Co.,LTDDP21i SYSTEM BLOCK Ver:BCPU Thermal Sensor+V3.3S,+V3.3ALPentium 4 Processor-M478 uFCPGA+VCC_IMVP,+VCC_VIDCK408 Clocking +V3.3SSS Clocking +V3.3SPage 6Page 6Page 3Backlight ConnectorPage 3,4,5PSB 400MHz LVDS DDR266 SODIMM0+V1.25S,+V2.5,+V3.3STFT+V3.3S+VDCPage 14Page 10,12,13Montara_GML732 uFCBGA+V3.3S,+V2.5 +V1.5S,+V1.2S +VCCP1.6-2.1GB/sDDR266 SODIMM1+V1.25S,+V2.5,+V3.3SCVGAPage 16R/G/BPage 11,12,13 LAN ControllerRTL8100BL+V3.3ALPage 7,8,9 IDE18X DVD+V5SRJ45HuB Interface 66HzPage 25IDE0(ATA66/100)3.5& HHD+V5SICH4-MPage 21 4x USB+V5S421 BGA USB2.0 [480Mb/s]+VCCP,+V3.3S +V3.3AL,+V1.5AL +V_RTC,+V1.5S +V5SPCMCIA CARDPCI BusCardBusTI PCI1410+V3.3SPage 17,18,19 FWH4Mbit+V3.3SPage 28BPage 22,23Amplifier+V5S SpeakerPage 20 Super I/OPC87391-VJG+V3.3SAC97 2.2AC'97CODEC+V5S,+V3.3SPage 30MirPage 29LPCKB Controller/ECPC87591-VLB+V3.3ALHSDL-3602+V3.3SPage 27MC'97MDC+V3.3SPage 26RJ11Page 27IEEE1284FIR +V5SPage 31MAX3243+V3.3SBlock Diagram Annotations & Infomation P4M CPU (1 of 2)(Host BUS) P4M CPU (2 of 2)(Power&GND) CPU Decoupling Clock Generator Montara-GML(Memory&GFX) Montara-GML(Host BUS) Montara-GML(Power & GND) DDR SO-DIMMs(1 of 2) DDR SO-DIMMs(2 of 2) DDR Series Termination DDR Parallel Termination LVDS & Inverter/LED CONN Blank CRT out ICH4-M (PCI/HUB/CPU) ICH4-M (MISC FUNCTION) ICH4-M (Power & GND) FWH(BIOS) IDE (HD & DVD-ROM) Cardbus TI PCI1410 CardBus CONNECTOR LPT/COM header/FIR LAN (RTL8100BL) KBC(PC87591E-VLB) SIO(PC87391-LPT /COM /IR) USB2.0 Ports AC'97 CODEC AC97 Audio IN/OUT/Amplifier MDC CONN /FAN CON POWER GOOD LOGIC ADAPTER & BATTERY IN +V3.3AS/ +V5AS/ +V12AS +V2.5/ +V1.25S +V1.5S/ +V1.2S COMMON POWER VCC_IMVP CHARGER THROUGH HOLE CLOCK Distribution Power On Sequence Reset Map Power On/Off Timings Revision History1 Revision History21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46DCBPage 27ParallelPage 27Serial TouchPAD KB Matrix Page Name Size Project Name Custom TOPSTAR TECHNOLOGY Andy Han BLOCK DIAGRAM P21i Rev BAADate: Monday, April 21, 2003 Sheet of 1 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5 4 3 2 154321Voltage Rails+VDCDI2C SMB Address DevicePrimary DC system power supply(12V-19V) Core/VTT voltage for processor & VTT for Montara-GML 1.2V for processor PLL and VID circuit 1.2V for Montara-GML core/hub interface 1.25V DDR Termination voltage 1.5V for hublink and ICH4-M core 1.5V always on power rail 2.5V power rail for DDR 3.3V always on power rail 3.3V main power rail 5V for ICH4M's VCC5Refsus 5V main power rail 12V always on power rail 12V main power rail RTL8100BL TI PCI1410 Clock Generator Spread Spectrum Clock SO-DIMM0 SO-DIMM1 24C02 Smart Bettery Thermal Diode Max1617Address01 010x 10 001x 01 011x xHexD2 D4 A0 A2 AE 16 9CBusSMB_ICH_S SMB_ICH_S SMB_ICH_S SMB_ICH_S SMB_ICH_S I2C_591 I2C_591MasterICH4-M ICH4-M ICH4-M ICH4-M ICH4-M EC ECD+VCC_IMVP +VCCP +VCC_VID +V1.2S +V1.25S +V1.5S +V1.5AL +V2.5 +V3.3AL +V3.3S +V5ALPCI DevicesDevice Device 2 Device 0 IDSEL# AD18 AD16 REQ/GNT# 2 / 2 1 / 1 InterruptCC+V5S +V12AL +V12SPIRQG# PIRQE#ns: Component marked &ns& is not stuff Power StatesBWake up EventsPME# from LAN RTL8100BL PME# from Cardbus LID switch from EC Power switch from ECstate Full ONsignalSLP_S1# SLP_S3# SLP_S4# HIGH LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW HIGH HIGH HIGH LOW LOW LOWSLP_S5#NO USE+V*AL ON ON ON ON ON OFF+V* ON ON ON OFF OFF OFF+V*S ON ON OFF OFF OFF OFFCLOCKS ON LOW OFF OFF OFF OFFKeyboard from ECBHIGH HIGH HIGH HIGH LOW LOWS1M(Power On Suspend) S3(Suspend to RAM) S4(Suspend to DISK) S5/Soft OffWith AC ING3With BatteryTOPSTAR TECHNOLOGY Andy Han Page Name Size A4 Project Name Annotations & Information P21i Rev AAAof Date: Monday, April 21, 2003 Sheet 2 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5 4 3 2 1ABCDEU1B H_A#16 H_A#15 H_A#14 H_A#13 H_A#12 H_A#11 H_A#10 H_A#9 H_A#8 H_A#7 H_A#6 H_A#5 H_A#4 H_A#3 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 L5 H3 J3 J4 K5 J1 AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 R5 A16# A15# A14# A13# A12# A11# A10# A9# A8# A7# A6# A5# A4# A3# ADSTB0# REQ4# REQ3# REQ2# REQ1# REQ0# A35# A34# A33# A32# A31# A30# A29# A28# A27# A26# A25# A24# A23# A22# A21# A20# A19# A18# A17# ADSTB1# ADS# AP0# AP1# BINIT# BNR# BPRI# DP3# DP2# DP1# DP0# DEFER# DRDY# DBSY# TESTHI8 TESTHI9 TESTHI10 BR0# CONTROL IERR# INIT# LOCK# MCERR# RESET# RS2# RS1# RS0# RSP# TRDY# HIT# HITM# +VCC_IMVP PGA479 socket 3mm PGA479 G1 AC1 V5 AA3 G2 D2 L25 K26 K25 J26 E2 H2 H5 U6 W4 Y3 H6 AC3 W5 G4 V6 AB25 F4 G5 F1 AB2 J6 F3 E3 H_BR3# H_BR2# H_BR1# H_ADS# {8} H_D#15 H_D#14 H_D#13 H_D#12 H_D#11 H_D#10 H_D#9 H_D#8 H_D#7 H_D#6 H_D#5 H_D#4 H_D#3 H_D#2 H_D#1 H_D#0 D25 J21 D23 C26 H21 G22 B25 C24 C23 B24 D22 C21 A25 A23 B22 B21 E21 E22 F21 H25 K23 J24 L22 M21 H24 G26 L21 D26 F26 E25 F24 F23 G23 E24 H22 G25 K22 J23 U1A D15# D14# D13# D12# D11# D10# D9# D8# D7# D6# D5# D4# D3# D2# D1# D0# DBI0# DSTBN0# DSTBP0# D31# D30# D29# D28# D27# D26# D25# D24# D23# D22# D21# D20# D19# D18# D17# D16# DBI1# DSTBN1# DSTBP1# D47# D46# D45# D44# D43# D42# D41# D40# D39# D38# D37# D36# D35# D34# D33# D32# DBI2# DSTBN2# DSTBP2# D63# D62# D61# D60# D59# D58# D57# D56# D55# D54# D53# D52# D51# D50# D49# D48# DBI3# DSTBN3# DSTBP3# T23 T22 T25 T26 R24 R25 P24 R21 N25 N26 M26 N23 M24 P21 N22 M23 P26 R22 P23 AA24 AA22 AA25 Y21 Y24 Y23 W25 Y26 W26 V24 V22 U21 V25 U23 U24 U26 V21 W22 W23 H_D#47 H_D#46 H_D#45 H_D#44 H_D#43 H_D#42 H_D#41 H_D#40 H_D#39 H_D#38 H_D#37 H_D#36 H_D#35 H_D#34 H_D#33 H_D#324H_BNR# H_BPRI#{8} {8}4ADDR GRP 0DATA GRP 0+VCC_IMVP H_DEFER# H_DRDY# H_DBSY# R686 R687 R688 {8} {8} {8} 56 56 56 R R0402 +VCC_IMVP H_IERR_PU# R689 56 R0402 {17} +VCC_IMVP {8} R690 51 R0402 H_RS#2 H_RS#1 H_RS#0 H_CPURST# {8} +V3.3S R685 220 R0402 H_BR0# {8} {8} H_D#[15:0] {8} H_DINV#0 {8} H_DSTBN#0 {8} H_DSTBP#0{8} {8}H_A#[16:3] H_ADSTB#0DATA GRP 2H_D#[47:32] {8} H_DINV#2 {8} H_DSTBN#2 {8} H_DSTBP#2 {8}{8}H_REQ#[4:0]3{8} H_A#[31:17] {8} H_ADSTB#1H_A#31 H_A#30 H_A#29 H_A#28 H_A#27 H_A#26 H_A#25 H_A#24 H_A#23 H_A#22 H_A#21 H_A#20 H_A#19 H_A#18 H_A#17H_INIT# H_LOCK#H_RS#2 H_RS#1 H_RS#0 H_TRDY# H_HIT# H_HITM#{8} {8} {8} {8}{8} H_D#[31:16] {8} H_DINV#1 {8} H_DSTBN#1 {8} H_DSTBP#1 R692 300 R0402H_D#31 H_D#30 H_D#29 H_D#28 H_D#27 H_D#26 H_D#25 H_D#24 H_D#23 H_D#22 H_D#21 H_D#20 H_D#19 H_D#18 H_D#17 H_D#16H_D#63 H_D#62 H_D#61 H_D#60 H_D#59 H_D#58 H_D#57 H_D#56 H_D#55 H_D#54 H_D#53 H_D#52 H_D#51 H_D#50 H_D#49 H_D#48ADDR GRP 1DATA GRP 1DATA GRP 33H_D#[63:48] {8} H_DINV#3 {8} H_DSTBN#3 {8} H_DSTBP#3 {8}+VCC_IMVP {8} {8} R693 56 R0402R691 2K R0402PGA479 socket 3mm PGA479 PM_THRM# {18}+VCC_IMVPQ77 3 6 300 R 1 2 MMDT3904 SC70_6 THERVCC R696 220 R0402+V3.3SR744 51 R0402R745 51 R0402 U1C AF22 AF23 AC26 AD26 C6 B6 B2 D1 E5 B5 Y4 B3 C4 A2 C3 AD6 AD5 A6 AD25 AB26 L24 P1R694 330 R0402 HOST CLK FSBSEL0 FSBSEL1 GHI# DPSLP# SLP# LEGACY CPU COMP0 COMP1 REF & COMP GTLREF3 GTLRER2 GTLREF1 GTLREF0 BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# TAP/ITP ITPCLKOUT0 ITPCLKOUT1 DBRESET TCK TDI TDO TMS TRST# SKTOCC# H_BSEL0 {6} H_BSEL1 {6} PM_CPUPERF# {18} H_DPSLP# H_CPUSLP# H_COMP0 R697 51.1,1% R0402 H_COMP1 R698 51.1,1% R} {17}H_PROCHOT#R695{6} CLK_CPU_BCLK {6} CLK_CPU_BCLK#BCLK0 BCLK1 ITP_CLK0 ITP_CLK1 A20M# FERR#/PBE# IGNNE# LINT0 LINT1 SMI# STPCLK#Place these 3 component together+VCC_IMVP1.H_THERMDA/C走线10 MILS,线线线走走, 然然然然然然然.C624 0.1uF/25V,Y5V C 2 3 4 5 6 7 8 NC4 VCC DXP DXN NC5 ADD1 GND1 GND2 NC3 STBY SMBCLK NC2 SMBDATA ALERT ADD0 NC1 16 15 14 13 12 11 10 9 THERADO22{17} H_A20M# {17} H_FERR# {17} H_IGNNE# {17} H_INTR {17} H_NMI {17} H_SMI# {17} H_STPCLK# R0402 DTD+_591 R989 0 ns H_THERMDA {26} DTD+_591 DTD-_591 R990 0 ns H_THERMDC {26} DTD-_591 R79 0 R0402 {18} PM_THRMTRIP# H_PROCHOT# R R704 R706 R707 R708 R709 56 56 56 56 56 56 R R R2.H_THERMDA/C走走走走19V走VGA走走走走走走C625 2200pF/25V,X7R C0402 +V3.3S R701 1K R0402 H_THERMDA H_THERMDCR near Pin &0.5',Trace=25mil length:&1.5 inch width&7mil,Space&10milH_BPM5 H_BPM4 H_BPM3 H_BPM2 H_BPM1 H_BPM0 R710 R711 GTLREFTHERMDA THERMDC THERMTRIP# PROCHOT# TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8AA21 AA6 F20 F6 AB4 AA5 Y6 AC4 AB5 AC6R699 49.9,1% R0402I2C_CLK I2C_DATA{26,39} {26,39}THERM+VCC_IMVPTEST/NCH_TESTHI5 AC23 H_TESTHI4 AC24 H_TESTHI3 AC20 H_TESTHI2 AC21 H_TESTHI1 AA2 H_TESTHI0 AD24 A22 A7 AD2 AD3 AE21 AF3 AF24 AF25 B1close to CPUC626 220pF/25V,X7R C0402close to DeviderC627 R700 1uF/10V,Y5V 100,1% CTHERAD1MAX1617AMEE SOP16_25_150R702 4.7K R0402+VCC_IMVP+VCC_IMVP 56 56+VCC_IMVPAddress:X+V3.3SR705 1K R0402AA20 H_ITPCLKOUT0 AB22 H_ITPCLKOUT1 AE25 ITP_DBRESET# D4 H_TDI C1 H_TDOR721 D5 H_TMS F7 E6 H_TRST# AF26 R723 680 R0402R R712 150 R713 27 ns R719 150 R R02 +VCC_IMVP R722 39 R0402R720 51 R0402 H_BPM0 H_BPM1 H_BPM2 H_BPM3 H_BPM4 H_BPM5R716 R714 R715 R717 R718 51 51 51 51 51 R R R04021TOPSTAR TECHNOLOGY Andy Han Page Name Size A3 Project Name Northwood Processor (1 of 2) P21i Rev A1PGA479 socket 3mm PGA479of Date: Monday, April 21, 2003 Sheet 3 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTARA B C D EABCDEU1D4+VCC_IMVP VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 F8 G21 G24 G3 G6 H1 H23 H26 H4 J2 J22 J25 J5 K21 K24 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5 K3432PGA479 socket 3mm1C62 1uF/10V,Y5V C0603HCPU1HCPU2HCPU3HCPU4PGA479 socket 3mm1 1K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182CPU_HOLE TH_200_112 nsCPU_HOLE TH_200_112 nsCPU_HOLE TH_200_112 nsCPU_HOLE TH_200_112 ns1111Size Project Name Rev P21i A3 1.0 of Date: Monday, April 21, 2003 Sheet 4 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTARA B C D E+A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD1 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AD4 AD8 AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE26 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80U1E A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 E14 E16 E18 E20 E8 F11 F13 F15 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VID4 VID3 VID2 VID1 VID0 VCCA VCCSENSE VCCIOPLL VSSA VSSSENSE VCCVID PWRGOOD F17 F19 F9 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 E12 AE1 AE2 AE3 AE4 AE5 AD20 A5 AE23 AD22 A4 AF4 AB23R6830 R0402VCC_IMVP_CPU_DPOWER3VSSH_VID4 H_VID3 H_VID2 H_VID1 H_VID0H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 TP24 TP25{38} {38} {38} {38} {38} L25 1 电电4.7UH 2 4.7uH/70mA,10% L1206+VCC_VID1 + C622 10uF/6.3V,X5R CT L26 10uF/6.3V,X5R CT3528 1 +VCC_VID 2 21 1ICTP ICTP电电4.7UH 2 4.7uH/70mA,10% L12062+VCC_IMVPR684 330 R0402 H_PWRGD {17}ShenZhen Topstar Technology Co.,LTDPage Name Northwood Processor (2 of 2)54321+VCC_IMVPD DC636 10uF/6.3V,X5R C1206C637 10uF/6.3V,X5R C1206C638 10uF/6.3V,X5R C1206C639 10uF/6.3V,X5R C1206C640 10uF/6.3V,X5R C1206C641 10uF/6.3V,X5R C1206C642 10uF/6.3V,X5R C1206C643 10uF/6.3V,X5R C1206C644 10uF/6.3V,X5R C1206C645 10uF/6.3V,X5R C1206+VCC_IMVP C646 10uF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R C1206CC+VCC_IMVP C656 10uF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R CuF/6.3V,X5R C1206+VCC_IMVPB BC666 10uF/6.3V,X5R C1206C667 10uF/6.3V,X5R C1206C668 10uF/6.3V,X5R C1206C669 10uF/6.3V,X5R C1206C670 10uF/6.3V,X5R C1206C671 10uF/6.3V,X5R C1206C672 10uF/6.3V,X5R C1206C673 10uF/6.3V,X5R C1206CPU Decoupling: 10uF/1206 x 38Page NameATOPSTAR TECHNOLOGY Andy Han CPU Decoupling P21i Rev AASize AProject Nameof Date: Monday, April 21, 2003 Sheet 5 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5 4 3 2 154321+V3.3S FB41 CLKVDD 1 1 C587 C588 C590 C591 C592 10uF/10V,Y5V 10uF/10V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V C C C 2FB42 CLKVDD48 300ohm@100MHz,1.5A FB C599 10uF/10V,Y5V 0.1uF/25V,Y5V C 1 2 1 22D+V3.3S300ohm@100MHz,1.5A C593 C594 C595 C596 C597 FBuF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V C C C0402 FB43 1 C601 0.1uF/25V,Y5V C.1uF/25V,Y5V Cohm@100MHz,1.5A FB.1uF/25V,Y5V C0402DCLKVDDA U47 1 8 14 19 32 37 46 50 2 3 40 55 54 25 34 53 28 43 VDDREF VDDPCI0 VDDPC11 VDD3V66_0 VDD3V66_1 VDD48 VDDCPU0 VDDCPU1 XTAL_IN XTAL_OUT F2 F1 F0 PWRDWN# PCI_STOP# CPU_STOP# VTT_PWRGD# MULTSEL0 SDATA SCLK 3V66_0 66SSC/48NonSSC IREF VSSIREF VSS0 VSS1 VSS6 VSS2 VSS3 VSS4 VSS5 2 27 45 44 49 48 52 51 24 23 22 21 7 6 5 18 17 16 13 12 11 PCI3 PCI2 R R CLK_LANPCI CLK_FWHPCI {25} {20} PCI6 PCI5 R R CLK_591PCI CLK_CBPCI {26} {22} 66BUF1 66BUF0 PCIF2 R658 33 R R656 33 R CLK_MCH66 CLK_ICH66 CLK_ICHPCI {7} {17} {17} CPU1 CPU1# CPU0 CPU0# R642 33 R R R R0402 VDDA VSSA CPUCLKT2 CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT0 CPUCLKC0 3V66_5 3V66_4 3V66_3 3V66_2 PCICLK_F2 PCICLK_F1 PCICLK_F0 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 26 1 C600 10uF/10V,Y5V C1206Place crystal within 500mils of CK-408Ncaps are internal to CK-408.+V3.3S C604 10pF/50V,NPO ns Y7 CMHz 4 2 XS4_5 R646 330 R0402 nsCCLK_XTALIN CLK_XTALOUT CK408_F2 R648 1K R0402 CK408_F1 CK408_F0CLK_CPU_BCLK {3} CLK_CPU_BCLK# {3} CLK_MCH_BCLK {8} CLK_MCH_BCLK# {8}CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK#R643 R64549.9,1% R,1% R R0402CR647 1K R0402ns10pF/50V,NPO C0402 1R650 49.9,1% R652 49.9,1%R653 1K R0402R654 0 R0402 ns R659 0 ns+V3.3SR75 10K R0402{18} PM_SLP_S1# {18} PM_STPPCI# R73 0 ns STPCPU#CLK_MCH66 CLK_ICH66 CLK_ICHPCIC606 C607 C608{3} {3}H_BSEL0 H_BSEL1R ns R0402{18,38} PM_STPCPU# R657 10K R0402 MULT010pF/50V,NPO C0402 ns 10pF/50V,NPO C0402 ns 10pF/50V,NPO C0402 ns{32} VR_PWRGD_CK408#{10,11,17} SMB_DATA_S R662 10K ns R,17} SMB_CLK_S29 30 33 CLK_66SSCCLK_591PCI CLK_CBPCIC609 C61010pF/50V,NPO C0402 ns 10pF/50V,NPO C0402 ns 10pF/50V,NPO C0402 ns 10pF/50V,NPO C0402 nsBR665 33 R040235 42 41 4 9 15 20 31 36 47CLK_LANPCI CLK_FWHPCIC612 C613CLK_IREFBSEL1 0 0 1 1MULT 1SEL0 0 1 0 1IREF 475 1%FUNCTION 166MHz Host 100MHz Host 200MHz Host 133MHz HostCLK CLK CLK CLKR668 475,1% R0402Keep Black Line Stub shortCK408 CLOCK SWING CONFIG 0.7 VOLTS +V3.3SPCICLK0 48MHz_USB 48MHz_DOT REF10 39 38 56PCI1 USB DOT CLK_REF0R674 0 R0402 nsC619 1uF/10V,Y5V C0603C620 0.1uF/25V,Y5V C0402 U48ICS950810BG TSSOP56_0D5_6D1R R R R RCLK_SIOPCI CLK_ICH48 DREFCLK CLK_SIO14 CLK_ICH14{27} {18} {7} {27} {18}CLK_SIOPCI CLK_ICH48 DREFCLK CLK_SIO14 CLK_ICH14C614 C615 C616 C618 C62110pF/50V,NPO ns 10pF/50V,NPO ns 10pF/50V,NPO ns 10pF/50V,NPO ns 10pF/50V,NPO nsC C C0402SSC_CLK_IN1 2CLKIN VDD GNDPD# SCLK SDATA8 7 6 5 SSC_SCLK R676 0PM_SLP_S1#{18} LCLKCTLA SMB_CLK_S LCLKCTLB SMB_DATA_S {7} {10,11,17} {7} {10,11,17}Keep Black Line Stub short-&A{7}DREFSSCLKR6 DREFSSCLK_D3 4SSC_SDATA R678R R02 R679 0 R0402 +V3.3STOPSTAR TECHNOLOGY Andy Han Page Name Size Project Name Custom Clock Generator P21i Rev AACLKOUT/FS_IN0 REF_OUT/FS_IN1 ICS91718AM SO8_50_150REFOUT R681 10K R0402R682 10K R0402of Monday, April 21,
Date: Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR4 3 2 15543U2B21{12} M_DATA[63:0] M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 AF2 AE3 AF4 AH2 AD3 AE2 AG4 AH3 AD6 AG5 AG7 AE8 AF5 AH4 AF7 AH6 AF8 AG8 AH9 AG10 AH7 AD9 AF10 AE11 AH10 AH11 AG13 AF14 AG11 AD12 AF13 AH13 AH16 AG17 AF19 AE20 AD18 AE18 AH18 AG19 AH20 AG20 AF22 AH22 AF20 AH19 AH21 AG22 AE23 AH23 AE24 AH25 AG23 AF23 AF25 AG25 AH26 AE26 AG28 AF28 AG26 AF26 AE27 AD27 AG14 AE14 AE17 AG16 AH14 AE15 AF16 AF17U2E SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32 SDQ33 SDQ34 SDQ35 SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63 SDQ64 SDQ65 SDQ66 SDQ67 SDQ68 SDQ69 SDQ70 SDQ71 SDQS0 SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7 SDQS8 SMA_A0 SMA_A1 SMA_A2 SMA_A3 SMA_A4 SMA_A5 SMA_A6 SMA_A7 SMA_A8 SMA_A9 SMA_A10 SMA_A11 SMA_A12 SMA_B1 SMA_B2 SMA_B4 SMA_B5 AG2 AH5 AH8 AE12 AH17 AE21 AH24 AH27 AD15 M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7M_DQS[7:0]{12}D+V1.5S R608 100K R0402R3 R5 R6 R4 P6 P5 N5 P2 N2 N3 M1 M5 P3 P4 T6 T5 L2 M2 G2 M3 K5 K1 K3 K2 J6 J5 H2 H1 H3 H4 H6 G3 J3 J2 K6 L5 L3 H5AC18 M_AA0 AD14 M_AA1 AD13 M_AA2 AD17 M_AA3 AD11 M_AA4 AC13 M_AA5 M_AA6 AD8 M_AA7 AD7 M_AA8 AC6 M_AA9 AC5 AC19 M_AA10 M_AA11 AD5 M_AA12 AB5 AD16 AC12 AF11 AD10 AC7 AB7 AC9 AC10 AD23 AD26 AC22 AC25 AD22 AD20 AC21 AC24 AD25 AB2 AA2 AC26 AB25 AC3 AD4 AC2 AD2 AB23 AB24 AA3 AB4 AE5 AE6 AE9 AH12 AD19 AD21 AD24 AH28 AH15 AC15 AC16 AB1 AJ22 AJ19 M_DM0 M_DM1 M_DM2 M_DM3 M_DM4 M_DM5 M_DM6 M_DM7 M_AB1 M_AB2 M_AB4 M_AB5 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# M_BS0# M_BS1# M_RAS# M_CAS# M_WE#M_AA0 M_AA[2:1] M_AA3 M_AA[5:4]{11,12,13} {10,13} {11,12,13} {10,13}DVOBD0 DVOBD1 DVOBD2 DVOBD3 DVOBD4 DVOBD5 DVOBD6 DVOBD7 DVOBD8 DVOBD9 DVOBD10 DVOBD11 DVOBCLK DVOBCLK# DVOBHSYNC DVOBVSYNC DVOBBLANK# DVOBFLDSTL DVOBCINTR# DVOBCCLKINT DVOCD0 DVOCD1 DVOCD2 DVOCD3 DVOCD4 DVOCD5 DVOCD6 DVOCD7 DVOCD8 DVOCD9 DVOCD10 DVOCD11BLUE BLUE# GREEN GREEN# RED RED# HSYNC VSYNC REFSET DDCACLK DDCADATA IYAM0 IYAM1 IYAM2 IYAM3 IYAP0 IYAP1 IYAP2 IYAP3 IYBM0 IYBM1 IYBM2 IYBM3 IYBP0 IYBP1 IYBP2 IYBP3 ICLKAM ICLKAP ICLKBM ICLKBP DDCPCLK DDCPDATAC9 D9 C8 D8 A7 A8 H10 J9 E8 B6 G9 G14 E15 C15 C13 F14 E14 C14 B13 H12 E12 C12 G11 G12 E11 C11 G10 D14 E13 E10 F10 B4 C5 G8 F8 A5 D12 F12 B12 A10DAC_BLUE DAC_GREEN DAC_RED DAC_HSYNC DAC_VSYNC{16} {16} {16} {16} {16} DAC_RED R607 137,1% R0402 DAC_GREENDAC_BLUEDACDAC_REFSET DAC_DDCACLK {16} DAC_DDCADATA {16} LVDS_YAM0 LVDS_YAM1 LVDS_YAM2 LVDS_YAP0 LVDS_YAP1 LVDS_YAP2 {14} {14} {14} {14} {14} {14}C371C372C373DR609 100K R0402Layout Note: 10mil width with 20mil spacing Short and Wide,Big Via to GND+V1.5S3.3pF/50V,NPO 3.3pF/50V,NPO 3.3pF/50V,NPO C C0402 ns ns nsDVOBFLDSTL DVOBCCLKINT R610 DVOBCINTRB2UD1M_AA[12:6] M_AB[2:1] M_AB[5:4] {10,13} {10,13} {11,13} {11,13} {10,13} {10,13} {11,13} {11,13}{11,12,13} {11,13} {11,13}100K R0402DAC_BLUE3C361 0.1uF/25V,Y5V C0402+V1.5S2DVOUD2C363 0.1uF/25V,Y5V C0402LVDSDDR SYSTEM MEMORYCSCKE0 SCKE1 SCKE2 SCKE3 SCS0# SCS1# SCS2# SCS3# SBA0 SBA1 SRAS# SCAS# SWE# SCMDCLK0 SCMDCLK0# SCMDCLK1 SCMDCLK1# SCMDCLK2 SCMDCLK2# SCMDCLK3 SCMDCLK3# SCMDCLK4 SCMDCLK4# SCMDCLK5 SCMDCLK5# SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7 SDM8 SRCVENOUT# SRCVENIN# SMRCOMP SMVSWINGL SMVSWINGHLVDS_CLKAM {14} LVDS_CLKAP {14}BAT54S SOT23DAC_GREEN31{11,12,13} {11,12,13} {11,12,13} {11,12,13} {11,12,13} {10} {10} {10} {10} +V1.5S {11} {11} {11} {11}DVOCCLK DVOCCLK# DVOCHSYNC DVOCVSYNC DVOCBLANK# DVOCFLDSTL MI2CCLK MI2CDATA MDVICLK MDVIDATA MDDCCLK MDDCDATA ADDID0 ADDID1 ADDID2 ADDID3 ADDID4 ADDID5 ADDID6 ADDID7 DVODETECT DPMS GVREF AGPBUSY# DVORCOMP 66IN RVSD0 RVSD1 RVSD2 RVSD3 RVSD4 GST2 GST1 GST0 RVSD8 RVSD9 RVSD10 RVSD11LVDS_DDCPCLK {14} LVDS_DDCPDATA {14} LVDS_BKLTCTL {14} LVDS_BKLTEN {14} LVDS_VDDEN {14} TP_LVDS_REFH TP_LVDS_REFL 1 1 TP26 TP27 TP28 ICTP ICTPBAT54S SOT23PANELBKLTCTL PANELBKLTEN PANELVDDEN LVREFH LVREFL LVBG LIBG DREFCLK DREFSSCLK LCLKCTLA LCLKCTLB DPWR# DPSLP# RSTIN# PWROKPlace close to the MCH(1.5&)+V1.5S1CC364 0.1uF/25V,Y5V C0402R616 100K R0402 GNDCLKSM_CLK_DDR0 M_CLK_DDR0# M_CLK_DDR1 M_CLK_DDR1# M_CLK_DDR3 M_CLK_DDR3# M_CLK_DDR4 M_CLK_DDR4#MI2CCLK MI2CDATA MDVICLK MDVIDATA MDDCCLK MDDCDATAK7 N6 N7 M6 P7 T7 E5 F5 E3 E2 G5 F4 G6 F6 L7 D5 F1LVDS_LVBG 1 LVDS_LIBG2 ICTP DAC_RED 3 +V3.3S 1 R620 10K R0402 +V1.5S MCH_EXTTS0UD3B7 B17 H9 C6 LCLKCTLB AA22 Y23 AD28 J11 D6 AJ1 B1 AH1 A2 AJ2 A28 AJ28 A29 B29 AH29 AJ29 AA9 AJ4 R621R617 1.5K,1% R0402 DREFCLK {6} DREFSSCLK {6} LCLKCTLA {6} LCLKCTLB {6}BAT54S SOT23R618 1K,1% R0402MISCADDDETECT {18} DPMS_CLK DVO_VREFH_DPSLP# {3,17} PCI_RST# {17,20,22,26} 0 R0402 IMVP_PWRGD {18,32}R623 1K,1% R0402 M_DM[7:0] {12}Place+V2.5C582 C1 near0.1uF/10V,X5R GMCH C0402{18} AGP_BUSY# MCH_GRCOMP {6} CLK_MCH66F7 D1 Y3 AA5 F2 F3 B2 B3 C2 C3 C4 D2 D3 D7 L4EXTTS0 MCHDETECTVSS NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11B{10,11} SM_VREFTP_M_RCVO# 1 TP_M_RCVI# 1NCR625 TP29 TP30 ICTP ICTP MCH_SMRCOMP 60.4,1% R.1uF/10V,X5R C0402 GST2 GST1 GST0MDDCCLK MDDCDATA MDVICLK MDVIDATA MI2CDATAR627 R628 R624 R626 R6312.2K 2.2K 2.2K 2.2K 2.2KR R RBAJ24 C584 0.1uF/10V,X5R C0402SMVREFMCH_SMVSWINGL MCH_SMVSWINGHPLACE near to PinC585 0.1uF/10V,X5R C0402 +V2.5 C586 0.1uF/10V,X5R C0402Layout Note: 12mil width with &10mil spacingR630 R0402PLACE together 60.4,1%RG82852GM SL6QG A1 BGA732PLACE near to PinAJ24+V2.5R632 R,1%MCH_GRCOMPRG82852GM SL6QG A1 BGA732MI2CCLKR629 2.2KLayout Note: 15mil width with &25mil spacingMCH_SMVSWINGHR633 150,1% R0402 MCH_SMVSWINGL R637 604,1% R0402R634 604,1% R0402Montara GML Strapping OptionHIGH LCLKCTLB ADDDETECT VTT=1.3V/P4M unUSE DVO FSB 400MHz 400MHz DDR 266MHz 200MHz LOW 1.05V/Banias(default) USE DVO(default) GFX CORE 133MHz 133MHzLayout Note: 10mil width with 20mil spacingADDDETECT GST2 GST1 GST0 LCLKCTLB R635 R636 R639 R640 R641 1K R 1K ns R0402 1K ns R0402 1K ns R0402 1K +V1.5SR638 150,1% R0402GST(2,1,0) 000(default) 010A+V3.3STOPSTAR TECHNOLOGY Andy Han Page Name Size Project Name Custom Montara-GML(Memory&GFX) P21i Rev AADate: Monday, April 21, 2003 Sheet 7 46 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5432154321Host Compensation & Reference VoltagesLayout Note: 15mil width&500mil长,with 20mil spacing 1uF靠靠Divider,0.1uF靠靠BGA pinU2A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 P23 T25 T28 R27 U23 U24 R24 U28 V28 U27 T27 V27 U25 V26 Y24 V25 V23 W25 Y25 AA27 W24 W23 W27 Y27 AA28 W28 AB27 Y26 AB28 R28 P25 R23 R25 T23 T26 AA26 AD29 AE29 H28 K28 B20 B18 J28 C27 E22 D18 K27 D26 E21 E18 J25 E25 B25 G19 F15 K21 J21 J17 Y28 Y22 C693 1uF/10V,X7R C0603 HUB_PD0 HUB_PD1 HUB_PD2 HUB_PD3 HUB_PD4 HUB_PD5 HUB_PD6 HUB_PD7 HUB_PD8 HUB_PD9 HUB_PD10 U7 U4 U3 V3 W2 W6 V6 W7 T3 V5 V4 W3 V2 T2 U2 W1 HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# ADS# HTRDY# DRDY# DEFER# HITM# HIT# HLOCK# BREQ0# BNR# BPRI# DBSY# RS0# RS1# RS2# K22 H27 K25 L24 J27 G28 L27 L23 L25 J24 H25 K23 G27 K26 J23 H26 F25 F26 B27 H23 E27 G25 F28 D27 G24 C28 B26 G22 C26 E26 G23 B28 B21 G21 C24 C23 D22 C25 E24 D24 G20 E23 B22 B23 F23 F21 C20 C21 G18 E19 E20 G17 D20 F19 C19 C17 F17 B19 G16 E16 C16 E17 D16 C18 L28 M25 N24 M28 N28 N27 P27 M23 N25 P28 M26 N23 P26 M27 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_ADS# H_TRDY# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_RS#0 H_RS#1 H_RS#2D{3}H_A#[16:3]H_D#[15:0]{3} +VCCPMCH_HXSWINGR588 301,1% R0402HXSWING and HYSWING +VCCP 15mil width&500mil长 with 25mil spacingMCH_HYSWING+VCCPDR589 301,1% R0402MCH_HDVREFR590 49.9,1% R0402R591 150,1% R0402R592 150,1% R0402R593 100,1% R0402{3}H_A#[31:17]H_D#[31:16] {3}+VCCP+VCCPHXRCOMP and HYRCOMP 18mil width&500mil长 with 25mil spacing R594MCH_HXRCOMP 27.4,1% R0402C{3} H_REQ#[4:0]CHOSTLayout Note: MCH_HXSWING and MCH_HYSWING should be 10mil traces with 20mil spacingMCH_HYSWING MCH_HXSWING{3} H_ADSTB#0 {3} H_ADSTB#1HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HADSTB0# HADSTB1# HCLKN HCLKP HYRCOMP HYSWING HXRCOMP HXSWING HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3# DINV0# DINV1# DINV2# DINV3# CPURST# HDVREF0 HDVREF1 HDVREF2 HCCVREF HAVREF HI_0 HI_1 HI_2 HI_3 HI_4 HI_5 HI_6 HI_7 HI_8 HI_9 HI_10 PSTRBS PSTRBF HLZCOMP PSWING HLVREFH_D#[47:32] {3} MCH_HCCVREFR595 49.9,1% R0402MCH_HAVREFR596 49.9,1% R0402R597 MCH_HYRCOMP 27.4,1% R0402R598 100,1% R0402R599 100,1% R0402{6} CLK_MCH_BCLK# MCH_HYRCOMP {6} CLK_MCH_BCLK MCH_HXRCOMPC571 0.1uF/10V,X5R C0402BMCH_HDVREFC572 {3} H_DSTBN#0 {3} H_DSTBN#1 0.1uF/10V,X5R C0402 {3} H_DSTBN#2 {3} H_DSTBN#3 {3} H_DSTBP#0 {3} H_DSTBP#1 {3} H_DSTBP#2 {3} H_DSTBP#3 {3} H_DINV#0 {3} H_DINV#1 {3} H_DINV#2 {3} H_DINV#3 {3} H_CPURST#H_D#[63:48] {3}Hub Interface Compensation & Reference Voltages+V1.2S+V1.2S R602 HUB_HLZCOMP 27.4,1% R3,1% R0402 MCH_HLVREF MCH_PSWING+V1.2SR600 49.9,1% R0402B350mVR606800mVR604 C691 0.1uF/10V,X5R 100,1% CC574 C575 0.1uF/10V,X5R 1uF/10V,X7R CMCH_HCCVREF MCH_HAVREF{17} HUB_PD[10:0] {17} HUB_PSTRB {17} HUB_PSTRB#C577 0.1uF/10V,X5R C0402AHUB_HLZCOMP MCH_PSWING C578 C579 MCH_HLVREF 1uF/10V,X7R 0.1uF/10V,X5R C C581 C580 0.01uF/25V,X7R 0.01uF/25V,X7R C{3} {3} {3} {3} {3} {3} {3} {3} {3} {3} {3} {3} {3} {3}100,1% R0402 GNDC692 0.1uF/10V,X5R C0402HUB I/FRG82852GM SL6QG A1 BGA732TOPSTAR TECHNOLOGY Andy Han Page Name Size A4 Project Name Montara-GML(Host BUS) P21i Rev AAof Date: Monday, April 21, 2003 Sheet 8 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5432154+V1.2S321DR585 1 R0603L22 112CBAJ26 VSS181 T9 VSS180 L6 VSS179 E28 VSS178 D28 VSS177C22 VSS176 AJ20 VSS174 AJ18 VSS173 AJ12 VSS172 AJ10 VSS171 AA29VSS170 W29 VSS169C1 G1 L1 U1 AA1 AE1 R2 AG3 AJ3 D4 G4 K4 N4 T4 W4 AA4 AC4 AE4 B5 U5 Y5 Y6 AG6 C7 E7 G7 J7 M7 R7 AA7 AE7 AJ7 H8 K8 P8 T8 V8 Y8 AC8 E9 L9 N9 R9 U9 W9 AB9 AG9 C10 J10 AA10 AE10 D11 F11 H11 AB11 AC11 AJ11 J12 AA12 AG12 A13 D13 F13 H13 N13 R13 U13 AB13 AE13 J14 P14 T14 AA14 AC14 D15 H15 N15 R15 U15 AB15 AG15 F16 J16 P16VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168T16 AA16 AE16 A17 D17 H17 N17 R17 U17 AB17 AC17 F18 J18 AA18 AG18 A19 D19 H19 AB19 AE19 F20 J20 AA20 AC20 A21 D21 H21 M21 P21 T21 V21 Y21 AA21 AB21 AG21 B24 F22 J22 L22 N22 R22 U22 W22 AE22 A23 D23 AA23 AC23 AJ23 F24 H24 K24 M24 P24 T24 V24 AA24 AG24 A25 D25 AA25 AE25 G26 J26 L26 N26 R26 U26 W26 AB26 A27 F27 AC27 AG27 AJ27 AC28 AE28 C29 E29 G29 J29 L29 N29 U291 C516 0.1uF/10V,X5R C.1uF/10V,X5R C.1uF/10V,X5R C.1uF/10V,X5R CuF/10V,Y5V C1206 + C510 10uF/10V,Y5V C1206 U2D J15 P13 T13 N14 R14 U14 P15 T15 AA15 N16 R16 U16 P17 T17 AA17 AA19 W21 H14 V1 Y1 W5 U6 U8 W8 V7 V9 D29 Y2 C532 0.1uF/10V,X5R C E1 J1 N1 E4 J4 M4 E6 H7 J8 L8 M8 N8 R8 K9 M9 P9 A9 B9 B8 A11 B11 G13 B14 J13 B15 F9 B10 D10 A12 A3 A4 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCCHL0 VCCHL1 VCCHL2 VCCHL3 VCCHL4 VCCHL5 VCCHL6 VCCHL7 VTTLF0 VTTLF1 VTTLF2 VTTLF3 VTTLF4 VTTLF5 VTTLF6 VTTLF7 VTTLF8 VTTLF9 VTTLF10 VTTLF11 VTTLF12 VTTLF13 VTTLF14 VTTLF15 VTTLF16 VTTLF17 VTTLF18 VTTLF19 VTTLF20 VTTHF0 VTTHF1 VTTHF2 VTTHF3 VTTHF4 G15 H16 H18 J19 H20 L21 N21 R21 U21 H22 M22 P22 T22 V22 Y29 K29 F29 AB29 A26 A20 A18 A22 A24 H29 M29 V29 AC1 AG1 AB3 AF3 Y4 AJ5 AA6 AB6 AF6 Y7 AA8 AB8 Y9 AF9 AJ9 AB10 AA11 AB12 AF12 AA13 AJ13 AB14 AF15 AB16 AJ17 AB18 AF18 AB20 AF21 AJ21 AB22 AF24 AJ25 AF27 AC29 AF29 AG29 AJ6 AJ8 AD1 AF1 +V1.2S_ASM C568 0.1uF/10V,X5R CU2C+VCCP1+V1.2SC518 0.1uF/10V,X5R C0402C519 0.1uF/10V,X5R C0402C520 2+10uF/10V,Y5V C1206C517 100uF/6.3V,TAN/LESR CT6032D+V1.2SC521 10uF/10V,Y5V C1206C522 0.1uF/10V,X5R C0402C523 0.1uF/10V,X5R C0402Resistor provided for power measurement(plane underneath resistor will have to be cut)C524 0.1uF/10V,X5R C0402Place these caps on the top sideMCH_PWR_VTTHF0 C525 0.1uF/10V,X5R MCH_PWR_VTTHF1 0.1uF/10V,X5R MCH_PWR_VTTHF2 C526 0.1uF/10V,X5R MCH_PWR_VTTHF3 C529 C528 MCH_PWR_VTTHF4 0.1uF/10V,X5R 0.1uF/10V,X5R C530 C C C0402 +V2.5C527 0.1uF/10V,X5R C L21 11POWERR0603+V1.2S_DPLLA0.10uH/250mA,10% + C531 LUF/6.3V,TAN CT7343_28 +V1.2S_DPLLBVCCAHPLL VCCAGPLL VCCADPLLA VCCADPLLB VCCDVO_0 VCCDVO_1 VCCDVO_2 VCCDVO_3 VCCDVO_4 VCCDVO_5 VCCDVO_6 VCCDVO_7 VCCDVO_8 VCCDVO_9 VCCDVO_10 VCCDVO_11 VCCDVO_12 VCCDVO_13 VCCDVO_14 VCCDVO_15 VCCADAC0 VCCADAC1 VSSADAC VCCALVDS VSSALVDS VCCDLVDS0 VCCDLVDS1 VCCDLVDS2 VCCDLVDS3 VCCTXLVDS0 VCCTXLVDS1 VCCTXLVDS2 VCCTXLVDS3 VCCGPIO_0 VCCGPIO_1VSS+V1.5S0.10uH/250mA,10% L0805 + C537 220UF/6.3V,TAN CTC538 0.1uF/10V,X5R C0402Layout note:Route VSSADAC trace to cap(no via at GMCH) Layout note:Route VSSALVDS trace to cap(no via at GMCH)+ C544 C543 10uF/10V,Y5V 100uF/6.3V,TAN/LESR C1206 CT6 1 0 R0805 2 + C549C545 0.1uF/10V,X5R C0402C546 0.1uF/10V,X5R C0402C553 0.1uF/10V,X5R C0402C554 0.01uF/25V,X7R C0402220UF/6.3V,TAN CT7343_28 nsC555 0.1uF/10V,X5R C0402C556 0.01uF/25V,X7R C0402+V2.5_QSM C557 4.7uF/10V,Y5V C0805 QSM_RL231+V2.52C550 C551 C552 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R C C0402+ C547 C690 10uF/10V,Y5V CuF/6.3V,TAN/LESR CT7343_281+V1.5S_ADAC单单单然+V2.5VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCQSM0 VCCQSM1 VCCASM0 VCCASM1CC533 0.1uF/10V,X5R C.1uF/10V,X5R C.1uF/10V,X5R C.1uF/10V,X5R C0402+V2.5C539 0.1uF/10V,X5R C0402C540 0.1uF/10V,X5R C0402C541 0.1uF/10V,X5R C0402C542 0.1uF/10V,X5R C04021+V2.5+ 2C559 2+47uF/6.3V,TAN CT3528C560 22uF/6.3V,TAN CT3216C561 0.1uF/10V,X5R C04020.68UH/150mA,10% C558 LuF/10V,X5R C R0603 L24 +V1.2SB1单单单然1C565 C564 0.1uF/10V,X5R 0.1uF/10V,X5R C0402 47uF/6.3V,TAN 22uF/6.3V,TAN C0402 CT3216 CT3528 + C562 + C563 2 +V3.3S 2RG82852GM SL6QG A1 C566 0.1uF/10V,X5R C04021111+C567 100uF/10V,TAN CT7343_281.0UH/300mA,10% L1211_8RG82852GM SL6QG A1 GNDC569 10uF/10V,Y5V C1206C570 0.1uF/10V,X5R C0402TOPSTAR TECHNOLOGY Andy Han Page Name Size A4 Project Name Montara-GML(Power & GND) P21i Rev AAAof Date: Monday, April 21, 2003 Sheet 9 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR54321543+V2.52+V5AL R742 0 R0603 21R743 1 1 2 ns 1+V5SVDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33D{12} M_AA_FR_0 {7,13} M_AA[2:1]DIM0 M_DATA_R_[63:0] {11,12,13} D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 201 GND0 202 GND1 5 7 13 17 6 8 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 71 73 79 83 72 74 80 84 M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63M_AA_FR_0 M_AA1 M_AA2 M_AA_FR_3 M_AA4 M_AA5 M_AA_FR_6 M_AA_FR_7 M_AA_FR_8 M_AA_FR_9 M_AA_FR_10 M_AA_FR_11 M_AA_FR_12 112 111 110 109 108 107 106 105 102 101 115 100 99 97 117 116 98 121 122 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13/DU BA0 BA1 BA2/DU CS0 CS1+V2.5 1{12} M_AA_FR_3 {7,13} M_AA[5:4]4 2 MEMVREF+ 1 1 3+V+R581 10K,1% R04020 R.1uF/25V,Y5V C.1k R0402 MEMVREF- 1 29 21 33 45 57 69 81 93 113 131 143 155 157 167 179 191 10 22 34 36 46 58 70 82 92 94 114 132 144 156 168 180 192D2U43O2G1212 SOT23_5 1SM_VREF{7,11}V-R582 10K,1% R0402 2C498 1000pF/25V,X7R C0402 5 GND 21 R583 2K R0402 ns R725 1 0 R0603 ns 2 +V5AL{12} M_AA_FR_[12:6] {12} M_BS0_FR# {12} M_BS1_FR# {7,13} {7,13} M_CS0# M_CS1#{11,12,13} M_DM_R_[7:0]CM_DM_R_0 M_DM_R_1 M_DM_R_2 M_DM_R_3 M_DM_R_4 M_DM_R_5 M_DM_R_6 M_DM_R_7{12} M_WE_FR# {12} M_CAS_FR# {12} M_RAS_FR# {7,13} {7,13} {7} {7} {7} {7} M_CKE0 M_CKE1119 120 118 96 95 35 37 160 158 89 91 M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 11 25 47 61 133 147 169 183 77 193 195 194 196 198 1 2 199 197 86 85 123 124 200WE CAS RAS CKE0 CKE1 CK0 CK0 CK1 CK1 CK2 CK2 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 SDA SCL SA0 SA1 SA2 VREF1 VREF2 VDDID VDDSPD SO-DIMM200,RVS,5.2mm DDR200RVS_4U54 and U43 Dual Layout+V2.5M_CLK_DDR0 M_CLK_DDR0# M_CLK_DDR1 M_CLK_DDR1#{11,12,13} M_DQS_R[7:0]12V-12 26 48 62 134 148 170 184 78DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM825U54KM4170/FAIRCHILD SOT23_5 SM_VREF O 1 nsCMEMVREFMEMVREF+4 3+V++ C499 150uF/6.3V,TAN/LESR CTB{6,11,17} SMB_DATA_S {6,11,17} SMB_CLK_S2C501 0.1uF/25V,Y5V C0402C502 0.1uF/25V,Y5V C0402C503 0.1uF/25V,Y5V C04021 C500 10uF/10V,Y5V C1206+V2.5BxSM_VREF +V3.3S C73 0.1uF/25V,Y5V C.1uF/25V,Y5V C0402C504 0.1uF/25V,Y5V C0402C505 0.1uF/25V,Y5V C0402C506 0.1uF/25V,Y5V C0402C507 0.1uF/25V,Y5V C0402C508 0.1uF/25V,Y5V C04023 15 27 39 51 63 75 87 103 125 137 149 159 161 173 185 4 16 28 38 40 52 64 76 88 90 104 126 138 150 162 174 186VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33close to DDR pinNC/DU/RESET NC/DU1 NC/DU2 NC/DU3 NC/DU4Layout note:Place capacitors between and near DDR connector if possible.GNDTOPSTAR TECHNOLOGY Andy Han Page Name DDR SO-DIMMs(1 of 2) P21i Rev A Size A4ASO-DIMM 0AProject Nameof Date: Monday, April 21, 2003 Sheet 10 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5432154+V2.532Layout note:Place capacitors between and near DDR connectors if possible.19 21 33 45 57 69 81 93 113 131 143 155 157 167 179 191 10 22 34 36 46 58 70 82 92 94 114 132 144 156 168 180 192VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33D{7,12,13} M_AA0 {7,13} M_AB[2:1] {7,12,13} M_AA3 {7,13} M_AB[5:4] {7,12,13} M_AA[12:6] M_AA0 M_AB1 M_AB2 M_AA3 M_AB4 M_AB5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 112 111 110 109 108 107 106 105 102 101 115 100 99 97 117 116 98 121 122 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13/DU BA0 BA1 BA2/DU CS0 CS1DIM1 M_DATA_R_[63:0] {10,12,13} D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 201 GND0 202 GND1 5 7 13 17 6 8 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 71 73 79 83 72 74 80 84 M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 +V2.5DC742 0.1uF/25V,Y5V C0402C743 0.1uF/25V,Y5V C0402C744 0.1uF/25V,Y5V C0402C745 0.1uF/25V,Y5V C0402C746 0.1uF/25V,Y5V C0402C747 0.1uF/25V,Y5V C0402+V2.5 1 + C485 150uF/6.3V,TAN/LESR CT 1{7,12,13} M_BS0# {7,12,13} M_BS1# {7,13} M_CS2# {7,13} M_CS3# {10,12,13} M_DM_R_[7:0]C487 C486 0.1uF/25V,Y5V 10uF/10V,Y5V CCM_DM_R_0 M_DM_R_1 M_DM_R_2 M_DM_R_3 M_DM_R_4 M_DM_R_5 M_DM_R_6 M_DM_R_7+V2.512 26 48 62 134 148 170 184 78 119 120 118 96 95 35 37 160 158 89 91DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE CAS RAS CKE0 CKE1 CK0 CK0 CK1 CK1 CK2 CK2 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 SDA SCL SA0 1010 SA1 SA2 VREF1 VREF2 VDDID VDDSPD NC/DU/RESET NC/DU1 NC/DU2 NC/DU3 NC/DU4 SO-DIMM200,STD,5.2mm DDR200STD_42C488 0.1uF/25V,Y5V C0402C489 0.1uF/25V,Y5V C0402C490 0.1uF/25V,Y5V C0402C491 0.1uF/25V,Y5V C0402C492 0.1uF/25V,Y5V C0402C493 0.1uF/25V,Y5V C0402C494 C495 0.1uF/25V,Y5V 0.1uF/25V,Y5V CC{7,12,13} M_WE# {7,12,13} M_CAS# {7,12,13} M_RAS# {7,13} M_CKE2 {7,13} M_CKE3 {7} {7} {7} {7} M_CLK_DDR3 M_CLK_DDR3# M_CLK_DDR4 M_CLK_DDR4#+V2.5C338 0.1uF/25V,Y5V C0402C302 0.1uF/25V,Y5V C0402C304 0.1uF/25V,Y5V C0402C384 0.1uF/25V,Y5V C0402C385 0.1uF/25V,Y5V C0402{10,12,13} M_DQS_R[7:0]B{6,10,17} SMB_DATA_S {6,10,17} SMB_CLK_S +V3.3S R579 1K R0402M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7+V2.511 25 47 61 133 147 169 183 77 193 195 194 196 198 1 2 199 197 86 85 123 124 200C380 0.1uF/25V,Y5V C0402C319 0.1uF/25V,Y5V C0402C322 0.1uF/25V,Y5V C0402C337 0.1uF/25V,Y5V C0402C312 0.1uF/25V,Y5V C0402B+V2.5001x{7,10}SM_VREFC359 0.1uF/25V,Y5V C0402+V3.3SC377 0.1uF/25V,Y5V C0402C348 0.1uF/25V,Y5V C0402C392 0.1uF/25V,Y5V C0402C406 0.1uF/25V,Y5V C0402C496 0.1uF/25V,Y5V C0402For DDR series R viasclose to DDR pin3 15 27 39 51 63 75 87 103 125 137 149 159 161 173 185 4 16 28 38 40 52 64 76 88 90 104 126 138 150 162 174 186VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33GNDTOPSTAR TECHNOLOGY Andy Han Page NameASO-DIMM 1SO-DIMM 1 is placed farther form the GMCH than SO-DIMM 0DDR SO-DIMMs(2 OF 2) P21i Rev ASize A4AProject Nameof Date: Monday, April 21, 2003 Sheet 11 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5432154321{7} {7} {7} {7,11,13}M_DATA[63:0] M_DQS[7:0] M_DM[7:0] M_AA[12:6]M_DATA_R_[63:0] {10,11,13} M_DQS_R[7:0] {10,11,13} M_DM_R_[7:0] {10,11,13} M_AA_FR_[12:6] {10} RN30 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 10 x8 RA0402_16DM_DATA0 M_DATA4 M_DATA1 M_DATA5 M_DQS0 M_DM0 M_DATA2 M_DATA6 M_DATA3 M_DATA7 M_DATA8 M_DATA12 M_DATA9 M_DATA13 M_DQS1 M_DM1RN21 1 3 5 7 9 11 13 15 RN23 1 3 5 7 9 11 13 15 RN26 1 3 5 7 9 11 13 15M_DATA_R_0 2 M_DATA_R_4 4 M_DATA_R_1 6 M_DATA_R_5 8 M_DQS_R0 10 M_DM_R_0 12 M_DATA_R_2 14 M_DATA_R_6 16 10 x8 RA 4 6 8 10 12 14 16 M_DATA_R_3 M_DATA_R_7 M_DATA_R_8 M_DATA_R_12 M_DATA_R_9 M_DATA_R_13 M_DQS_R1 M_DM_R_1Layout Note: 可可Swap可Group可可可 可可可16P8R可可8P4R走单可0402电可M_DQS4 M_DM4 M_DATA34 M_DATA38 M_DATA35 M_DATA39 M_DATA40 M_DATA44M_DQS_R4 M_DM_R_4 M_DATA_R_34 M_DATA_R_38 M_DATA_R_35 M_DATA_R_39 M_DATA_R_40 M_DATA_R_44D10 x8 RA 4 6 8 10 12 14 16 M_DATA_R_16 M_DATA_R_20 M_DATA_R_17 M_DATA_R_21 M_DQS_R2 M_DM_R_2 M_DATA_R_18 M_DATA_R_22CM_DQS2 M_DM2 M_DATA18 M_DATA22M_DATA16 M_DATA20 M_DATA17 M_DATA21M_DATA51 M_DATA55 M_DATA56 M_DATA60 M_DATA57 M_DATA61 M_DQS7 M_DM7RN22 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16M_DATA_R_51 M_DATA_R_55 M_DATA_R_56 M_DATA_R_60 M_DATA_R_57 M_DATA_R_61 M_DQS_R7 M_DM_R_7M_DATA10 M_DATA14 M_DATA11 M_DATA1510 x8 RA0402_16 RN25 M_DATA_R_10 1 2 M_DATA_R_14 3 4 M_DATA_R_11 5 6 M_DATA_R_15 7 8 10 x4 RA0402_8 RN24 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 10 x8 RA0402_16 RN39 1 2 3 4 5 6 7 8 10 x4 RA0402_8 RN28 1 2 3 4 5 6 7 8 10 x4 RA0402_8M_DATA58 M_DATA62 M_DATA59 M_DATA6310 x8 RA0402_16 RN31 1 2 3 4 5 6 7 8 10 x4 RA0402_8 RN38 1 3 5 7 10 x4 R575 10 R577 10CM_DATA_R_58 M_DATA_R_62 M_DATA_R_59 M_DATA_R_63M_DATA19 M_DATA23 M_DATA24 M_DATA28 M_DATA25 M_DATA29 M_DQS3 M_DM3M_DATA_R_19 M_DATA_R_23 M_DATA_R_24 M_DATA_R_28 M_DATA_R_25 M_DATA_R_29 M_DQS_R3 M_DM_R_3M_AA11 M_AA9 M_AA12 M_AA8M_AA_FR_11 2 M_AA_FR_9 4 M_AA_FR_12 6 M_AA_FR_8 8 RA02 R0402 M_CAS_FR# M_WE_FR# {10} {10}{7,11,13} M_CAS# {7,11,13} M_WE#BM_DATA26 M_DATA30 M_DATA27 M_DATA31 M_DATA32 M_DATA36 M_DATA33 M_DATA37M_DATA_R_26 M_DATA_R_30 M_DATA_R_27 M_DATA_R_31 M_DATA_R_32 M_DATA_R_36 M_DATA_R_33 M_DATA_R_37{7,11,13} {7,11,13} {7,11,13} {7,11,13}M_AA0 M_BS1# M_RAS# M_BS0#M_AA0RN40 1 3 5 7 10 x42 4 6 8 RA0402_8M_AA_FR_0M_AA_FR_0 M_BS1_FR# M_RAS_FR# M_BS0_FR#{10} {10} {10} {10}B{7,11,13} M_AA3M_AA3 M_AA6 M_AA7 M_AA10R933 10 R935 10 R937 10 R941 10R RM_AA_FR_3 M_AA_FR_6 M_AA_FR_7 M_AA_FR_10M_AA_FR_3{10}M_DATA41 M_DATA45 M_DQS5 M_DM5 M_DATA42 M_DATA46 M_DATA43 M_DATA47RN29 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 10 x8 RA0402_16M_DATA_R_41 M_DATA_R_45 M_DQS_R5 M_DM_R_5 M_DATA_R_42 M_DATA_R_46 M_DATA_R_43 M_DATA_R_47Address /control signal use Topology 2 of RDDPTOPSTAR TECHNOLOGY Andy Han Page Name Size A4 Project Name DDR Series Termination P21i Rev AAM_DATA48 M_DATA52 M_DATA49 M_DATA53 M_DQS6 M_DM6 M_DATA50 M_DATA54RN27 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 10 x8 RA0402_16M_DATA_R_48 M_DATA_R_52 M_DATA_R_49 M_DATA_R_53 M_DQS_R6 M_DM_R_6 M_DATA_R_50 M_DATA_R_54Aof Date: Monday, April 21, 2003 Sheet 12 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR54321543Layout Note: 可可Swap可Group可可可 可可可16P8R可可8P4R走单可0402电可21Layout note:Place one cap close to every 2 pullup resistors terminated to +V1.25+V1.25S M_DQS_R0 M_DM_R_0 M_DATA_R_2 M_DATA_R_6 M_DATA_R_3 M_DATA_R_7 M_DATA_R_8 M_DATA_R_12 RN10 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 56 X8 RA 4 6 8 10 12 14 16 56 X8 RA 4 6 8 10 12 14 16 56 X8 RN12 RA 4 6 8 10 12 14 16 56 X8 RA0402_16 RN15 2 4 6 8 10 12 14 16 56 X8 RA0402_16 RN16 2 4 6 8 10 12 14 16 56 X8 RA0402_16 RN18 2 4 6 8 10 12 14 16 56 X8 RA 4 6 8 10 12 14 16 56 X8 RA 6 4 2 RN17 56 x4 7 5 3 1 RA0402_8 M_DATA_R_5 M_DATA_R_1 M_DATA_R_4 M_DATA_R_0 +V1.25S每4可R每可电每每每可0.01uF,每可0.1uFC432 0.1uF/25V,Y5V C.01uF/25V,X7R C.1uF/25V,Y5V C.01uF/25V,X7R C.1uF/25V,Y5V C.01uF/25V,X7R C.1uF/25V,Y5V C0402DDM_DATA_R_9 M_DATA_R_13 M_DQS_R1 M_DM_R_1 M_DATA_R_10 M_DATA_R_14 M_DATA_R_11 M_DATA_R_15RN9 1 3 5 7 9 11 13 15RN19 56 x4 M_DATA_R_63 1 2 M_DATA_R_59 3 4 M_DATA_R_62 5 6 M_DATA_R_58 7 8 RA0402_8 RN35 56 x4 1 3 5 7 2 4 6 8 RA7 56 R570 R0402 M_AA9C425 0.01uF/25V,X7R C0402C447 0.1uF/25V,Y5V C0402C426 0.01uF/25V,X7R C0402C427 0.1uF/25V,Y5V C0402C428 0.1uF/25V,Y5V C0402C429 0.1uF/25V,Y5V C0402C430 0.1uF/25V,Y5V C0402C431 0.1uF/25V,Y5V C0402M_DATA_R_31 M_DATA_R_27 M_DATA_R_30 M_DATA_R_26CM_DATA_R_16 M_DATA_R_20 M_DATA_R_17 M_DATA_R_21 M_DQS_R2 M_DM_R_2 M_DATA_R_18 M_DATA_R_22RN13 1 3 5 7 9 11 13 15M_DATA_R_[63:0] {10,11,12} M_AA[12:6] {7,11,12} M_AA[5:4] {7,10} M_DM_R_[7:0] {10,11,12} M_DQS_R[7:0] {10,11,12} M_AA[2:1] {7,10}C437 0.1uF/25V,Y5V C0402M_AA12 56 R0402 RN14 56 x4 M_DATA_R_37 1 2 M_DATA_R_33 3 4 M_DATA_R_36 5 6 M_DATA_R_32 7 8 RA0402_8 RN36 56 x4 1 2 3 4 5 6 7 8 RA0402_8 RN11 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 56 X8 RA0402_16 RN8 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 56 X8 RA0402_16 M_AB2 M_WE# M_BS0# M_AA3 M_AB1 {7,11} {7,11,12} {7,11,12} {7,11,12} {7,11} M_CS2# M_CS0# M_CS3# M_CAS# M_RAS# M_CS1# M_BS1# M_AA0 {7,11} {7,10} {7,11} {7,11,12} {7,11,12} {7,10} {7,11,12} {7,11,12} M_AA5 M_AA4 M_AA7 M_AB5 {7,11}C438 0.1uF/25V,Y5V C0402C439 0.01uF/25V,X7R C0402C440 0.01uF/25V,X7R C0402C442 0.01uF/25V,X7R C441 0.1uF/25V,Y5V CC443 0.01uF/25V,X7R C0402C444 0.01uF/25V,X7R C0402CC449 0.01uF/25V,X7R C.1uF/25V,Y5V C.01uF/25V,X7R C.1uF/25V,Y5V C.1uF/25V,Y5V C.01uF/25V,X7R C.1uF/25V,Y5V C.01uF/25V,X7R C0402M_DATA_R_19 M_DATA_R_23 M_DATA_R_24 M_DATA_R_28 M_DATA_R_25 M_DATA_R_29 M_DQS_R3 M_DM_R_31 3 5 7 9 11 13 15C445 0.1uF/25V,Y5V C0402C462 0.01uF/25V,X7R C0402C463 0.01uF/25V,X7R C0402C464 0.01uF/25V,X7R C0402C465 0.01uF/25V,X7R C0402C466 0.01uF/25V,X7R C0402C467 0.1uF/25V,Y5V C0402C468 0.1uF/25V,Y5V C0402M_DQS_R4 M_DM_R_4 M_DATA_R_34 M_DATA_R_38 M_DATA_R_35 M_DATA_R_39 M_DATA_R_40 M_DATA_R_441 3 5 7 9 11 13 15M_AA0C458 0.1uF/25V,Y5V C0402C473 0.1uF/25V,Y5V C0402C474 0.01uF/25V,X7R C0402C475 0.01uF/25V,X7R C0402BC476 0.01uF/25V,X7R C0402M_DATA_R_51 M_DATA_R_55 M_DATA_R_56 M_DATA_R_60 M_DATA_R_57 M_DATA_R_61 M_DQS_R7 M_DM_R_71 3 5 7 9 11 13 15M_AA10 M_AA3 M_AA1 M_AA2BM_DATA_R_41 M_DATA_R_45 M_DQS_R5 M_DM_R_5 M_DATA_R_42 M_DATA_R_46 M_DATA_R_43 M_DATA_R_471 3 5 7 9 11 13 15RN41 56 x4 1 2 3 4 5 6 7 8 RA0402_8C452 0.01uF/25V,X7R C0402 M_CKE0 M_CKE1 M_CKE2 M_CKE3 {7,10} {7,10} {7,11} {7,11}C461 0.1uF/25V,Y5V C0402C459 0.1uF/25V,Y5V C0402 GNDC460 0.01uF/25V,X7R C0402C469 0.1uF/25V,Y5V C0402C470 0.1uF/25V,Y5V C0402C471 0.01uF/25V,X7R C0402C472 0.1uF/25V,Y5V C0402AM_DATA_R_48 M_DATA_R_52 M_DATA_R_49 M_DATA_R_53 M_DQS_R6 M_DM_R_6 M_DATA_R_50 M_DATA_R_54RN20 1 3 5 7 9 11 13 15RN37 56 x4 1 2 3 4 5 6 7 8 RA0402_8M_AA6 M_AA8 M_AA11M_AB4{7,11}+V1.25STOPSTAR TECHNOLOGY Andy HanC477 10uF/10V,Y5V C C478 10uF/10V,Y5V 10uF/10V,Y5V CPage Name Size A4 Project NameDDR Parallel Termination P21i Rev AAof Date: Monday, April 21, 2003 Sheet 13 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5432154321+V3.3SQ75 NDS356AP 2 3 SOT23LCDVDD rising time is 470uSFB36 1 2 LCDVDD 300ohm@100MHz,1.5A C417 FB0805 1uF/10V,Y5V C0603LCDVDD R81 LCDVDD LCDVDD VLCD 0 R0603500mALCDCON 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 42 41 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39500mAC418 +V3.3S R741 2.2K R0402 nsR562 3 LCDVDD_EN# 1M R0K RN7002 SOT23350mA{7} LVDS_CLKAP {7} LVDS_CLKAM LVDS_YAM2 LVDS_YAP2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40C419 0.01uF/25V,X7R C0402 110uF/10V,Y5V C1206DC420 0.01uF/25V,X7R C0402 nsR565 2.2K R0402R566{7} 2.2K {7} R0402LVDS_YAM0 LVDS_YAP0 LVDS_YAM1 LVDS_YAP1 LID_ID1{7} {7} {7} {7}D{7} LVDS_VDDENR564 1K R04021 2{7} LVDS_DDCPDATA {7} LVDS_DDCPCLK LID_ID0 C76 100pF/50V,NPO 100pF/50V,NPO C {26} +VDC C77 BAT_STATE_LED CHARGE_LED PWRSTATE_LEDHD_LED# DVD_LED# NUMLED# Bright_adj BKLT_ON{21} {21} {26}CAPLED#500mAF3 1 0 R0603FB39 2 INVT_VDD C424 10uF/25V,X5R C.1uF/25V,Y5V C0402+V3.3S300ohm@100MHz,1.5A FB0805+V3.3SCLOSE TO INTCON42 41500mAPanel CON. 2x20Pin CNS40_LCDCHigh : Enable Low : DisableD52 {7} LVDS_BKLTEN {18,26,32} PM_PWROK {26} LIDSW# 2 2 2 D53 D54 1N4148WS 1 SOD323 1 1N4148WS SOD323 ns 1 SOD323 1N4148WSR567 10K R0402 FB37 LIGHT_ON 1 2 BKLT_ONR94 20K R0402R84 20K R0402LID_ID0 LID_ID1LID_ID0 LID_ID1{18} {18}C300ohm@100MHz,0.3A FB R.1uF/25V,Y5V C0402 Bright C423 1000pF/25V,X7R C0402{26} BRIGHTNESSBrightness:0V~3.3V{7} LVDS_BKLTCTLR2410 R0402 nsDVD_LED# NUMLED# CAPLED# HD_LED# BAT_STATE_LED CHARGE_LED PWRSTATE_LEDCB5 CB7 CB8 CB9 CB11 CB10 CB11000pF/25V,X7R CpF/25V,X7R CpF/25V,X7R CpF/25V,X7R CpF/25V,X7R CpF/25V,X7R CpF/25V,X7R C0402ID1 1 1 0 0ID0 1 0 1 0AU 14.1'A Grade TFT AU 14.1'B Grade TFT+V5Sfor EMI,close to connector+V3.3AL C183 0.1uF/25V,Y5V C0402 ns R292 1M R0402 ns 3 2 C217 0.22uF/10V,Y5V C0402 Q60 ns SOT23 2N7002 ns 2B1 +V3.3AL C511 0.1uF/25V,Y5V C0402 nsBU34 SOT23_5 4 R257Power on: llight Suspend:blink0 R0402 ns R258 0 R0402 1 +V3.3AL CB4 0.1uF/25V,Y5V C} CHG_LED CHG_LED 1 2 2 1 +V3.3AL3Q57 2N2222 SOT23 R220CB2 0.1uF/25V,Y5V C0402U44254 Bright PWRSTATE_LED 3+ns G1212 SOT23_5 O 1V+FB45 1 2 Bright_adjSN74AHC1G04DBV ns 1 3 {26} POWERLED {26} BTL_LED{26} POWERLED1 2BTL_LEDQ58 2N2222 SOT23CB3 0.1uF/25V,Y5V C04020 R040225V-Orange colorR726 1 0 R0603 2300ohm@100MHz,0.3A FB00pF/25V,X7R C04023f=1/（2∏RC（ARED colorR222 0 R0402 BAT_STATE_LEDQ59 2N2222 SOT23 R223 0 R0402 CHARGE_LED Page Name Size Project Name CustomTOPSTAR TECHNOLOGY Andy Han LVDS & Inverter CONN P21i Rev AAGreen ColorDate: Monday, April 21, 2003 Sheet 14 46 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5 4 3 2 154321DDCCBBATOPSTAR TECHNOLOGYAAndy HanPage NameTV Encoder(FS454 or CH7008)Size A3Project NameP21iRev Aof Date: Monday, April 21, 2003 Sheet 15 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5 4 3 2154321+V5S R526 470 R0603VGA CONNECTORGND_CRT GND_CRT VGA 19 20 21 C366 1 SOT23 3 UD4 BAT54S 2 C365 0.1uF/25V,Y5V C0402 +V5SDDFB25175ohm@100MHz,0.5A 2 FB0603 CONNECTOR TOP VIEWC362 0.1uF/25V,Y5V C040275ohm电可电 电 走走可走37.5ohm{7} DAC_RED {7} DAC_GREEN {7} DAC_BLUE R53075ohm电可然 电 走走可走75ohm1FB26 75ohm@100MHz,0.5AGND_CRT ROUT 2 FB0603 75ohm@100MHz,0.5A GOUT 1 2 FB27 FB0603 75ohm@100MHz,0.5A BPUT 1 2 FB28 FB C369 C370R531R532 75,1% R C415 C416 3.3pF/50V,NPO 3.3pF/50V,NPO 3.3pF/50V,NPO C C04026 1 7 2 8 3 9 4 10 5GND R GND NC11 12 13 14 15C367 100pF/50V,NPO 100pF/50V,NPO C R527 R528 39 100 39 R 100SDA G GND B HSYNC NC NC VSYNC GND GND shell CLK shellR5VDDCDA HSYNC VSYNC 5VDDCCKR529 R53316 17 1875,1% R040275,1% R04023.3pF/50V,NPO 3.3pF/50V,NPO 3.3pF/50V,NPO C C0402VGACON VGADM C374 C375 100pF/50V,NPO 100pF/50V,NPO C3+V5S 2 C376 0.1uF/25V,Y5V C0402C1CGND_CRT +V3.3S +V5SGND_CRTGND_CRTUD5 BAT54S SOT23R538 2.7K R0402R537 2.7K R0402+V5S C695 0.1uF/25V,Y5V C 4 GND SN74AHC1G08DBV SOT23_5 3 VSYNC 1 2 5 U56 VCC 4 GND SN74AHC1G08DBV SOT23_5 3 +V5S C381 0.1uF/25V,Y5V C040211 {7} DAC_VSYNC 3 5VDDCDA 2VCC{7} DAC_HSYNCHSYNC{7} DAC_DDCADATA2Q74 2N7002 SOT23R542B0 nsR0402R5430 nsR0402B+V3.3S+V5SR534 R536 2.7K RK R R0805 ns 0 R0805 nsR340 1{7} DAC_DDCACLK23 Q73 2N7002 SOT235VDDCCK GND_CRTATOPSTAR TECHNOLOGY Andy Han Page Name Size A3 Project Name CRT/TV out P21i Rev AAof Date: Monday, April 21, 2003 Sheet 16 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR5 4 3 2 154321+V3.3S {22,25} PCI_AD[0:31] U3A R464 R466 R467 R468 R469 R470 R471 R473 R476 R478 R480 R482 R484 R487 R489 R492 R493 R494 R495 R496 R497 R498 R499 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K R R R R R R R R R R R R0402 PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# INT_IRQ14 INT_IRQ15 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 {22,25} {22,25} {22,25} {22,25} PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# 1 ICTP PCI_GNT3# PCI_GNT4# PCI_REQ0# PCI_REQ3# PCI_REQ4# H5 J3 H3 K1 G5 J4 H4 J5 K2 G2 L1 G4 L2 H2 L3 F5 F4 N1 E5 N2 E3 N3 E4 M5 E2 P1 E1 P2 D3 R1 D2 P4 J2 K4 M4 N4 C1 E6 A7 B7 D6 B1 A2 B3 C7 B6 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_GNT4# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GPIO0/REQA# PCI_GPIO1/REQB_L/REQ5# PCI_GPIO16/GNTA# PCI_GPIO17/GNTB_L/GNT5# PCI_IRDY# PCI_PAR PCI_PERR# PCI_LOCK# PCI_PME# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# SM_INTRUDER# SMLINK0 SMLINK1 SMB_CLK SMB_DATA SMB_ALERT#/GPIO11 System Managent I/F CPU_A20GATE CPU_A20M# CPU_DPSLP# CPU_FERR# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_PWRGOOD CPU_RCIN# CPU_SLP# CPU_SMI# CPU_STPCLK# HUB_PD0 HUB_PD1 HUB_PD2 HUB_PD3 HUB_PD4 HUB_PD5 HUB_PD6 HUB_PD7 HUB_PD8 HUB_PD9 HUB_PD10 HUB_PD11 HUB_CLK HUB_PSTRB# HUB_PSTRB HUB_RCOMP HUB_VREF HUB_VSWING INT_APICCLK INT_APICD0 INT_APICD1 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE#/GPIO2 INT_PIRQF#/GPIO3 INT_PIRQG#/GPIO4 INT_PIRQH#/GPIO5 INT_IRQ14 INT_IRQ15 INT_SERIRQ EEP_CS EEP_DIN EEP_DOUT EEP_SHCLK LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN_JCLK LAN_RSTSYNC LAN_RST# W6 AC3 AB1 AC4 AB4 AA5 Y22 AB23 U23 AA21 W21 V22 AB22 V21 Y23 U22 U21 W23 V23 L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21 T21 N20 P21 R23 M23 R22 J19 H19 K20 D5 C2 B4 A3 C8 D7 C3 C4 AC13 AA19 J22 D10 D11 A8 C12 A10 A9 A11 B10 C10 A12 C11 B11 Y5 HUB_PD0 HUB_PD1 HUB_PD2 HUB_PD3 HUB_PD4 HUB_PD5 HUB_PD6 HUB_PD7 HUB_PD8 HUB_PD9 HUB_PD10 HUB_PD11 CLK_ICH666SM_INTRUDER# R463 0 R R0402 SMB_ALERT# +VCCP54R461 2K R0402 H_INIT#_DQ R462 300 R0402+V3.3SMMDT3904SMB_CLK SMB_DATA123DICH4-MCPU I/FH_A20GATE H_A20M# H_DPSLP# H_IGNNE# H_INTR H_NMI H_PWRGD H_RCIN# H_CPUSLP# H_SMI# H_STPCLK#{26} {3} {3,7} {3} {3} {3} {4} {26} {3} {3} {3}R738 56 R0402 H_FERR# {3} R479 300 R0402 5FWH_INIT#{20}DQ72 3 6 2 MMDT3904 SC70_6 4 1PART ACLOSE TOGETHERR4860 R0402H_INIT#{3}+V1.5S +V1.5S R500 48.7,1% R3,1% R0402+V3.3AL R503 R505 R506 +V_RTC R509 100K SM_INTRUDER# R0402 10K R0402 SMB_ALERT# 2.2K 2.2K R SMB_CLK SMB_DATAHUB I/FPCI I/FHUB_PD[10:0] {8} R502 {6} 56 R0402CTP32 {22} PCI_GNT1# {25} PCI_GNT2# 1 TP9 ICTP 1 TP10 ICTP {22} PCI_REQ1# {25} PCI_REQ2#HUB_RCOMP_ICH HUB_VREF_ICH HUB_VSWING_ICHHUB_PSTRB# {8} HUB_PSTRB {8}PLACE RCOMP resistor within 0.5& of ICH pad using a thick trace RCOMP R should be 2/3 board impedance.0.35V+-8%C355 0.01uF/25V,X7R C0402 +V1.5S C356 0.1uF/25V,Y5V C0402R504 75,1% R0402CInterrupt I/F+V3.3S R514 ns R518 ns 2.2K RK R0402 SMB_CLK_S SMB_DATA_SINT_APICCLK R507 0 INT_APICD0 R508 10K INT_APICD1 R510 10K INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQF#R R04020.80V+-8%C357 0.01uF/25V,X7R C.1uF/25V,Y5V C0402R511 130,1% R0402INT_PIRQE# {22} INT_PIRQG# {25} INT_PIRQH# {22} {21} {21} INT_SERIRQ {22,26,27} R519 R516 150,1% R0402+V3.3S TP11 ICTP 1{6} CLK_ICHPCI {22,25} PCI_DEVSEL# {22,25} PCI_FRAME# R739 R740 {18} PCI_GNTA# {22,25} PCI_IRDY# {22,25} PCI_PAR {22,25} PCI_PERR# PCI_PME# R393 R0402{25,26} PCI_PME#{22,25} PCI_SERR# {22,25} PCI_STOP# {22,25} PCI_TRDY#BLAN I/FP5 M3 F1 8.2K R.2K R C5 L5 G1 L4 PCI_LOCK# M2 0 W2 PCI_RST# U5 K5 F3 F2INT_IRQ14 INT_IRQ15+V5SEEPROM I/FC360EEP_DOUT{18}8.2K +V3.3S R0402HUB INTERFACE VSWING VOLATAGEHUB INTERFACE LAYOUT: Route signals with 4/8 trace/space routing.Signals must match +/-0.1& of HUB_STB/STB# signals.0.1uF/25V,Y5V C0402R521 10K R0402BFW82801DBM SL6DN B1 BGA421+V3.3S Q86 2N7002 SOT23 3 PCI_PME# 1The Bus switch prevents Leakage of the SMBus into +V5S devices powered on the switched rail.100 R524 R0402 SMB_CLK {6,10,11} SMB_CLK_S U38 1 2 3 4 OE1# 1A 1B GND VCC OE2# 2B 2A 8 7 6 5 R525C480 0.1uF/25V,Y5V C{22}CB_PME#2R0402 SMB_DATA_S {6,10,11}SMB_DATA+V3.3AL +V3.3S U33 1 2 3 4 A0 A1 A2 GND VDD WP SCL SDA 8 7 6 5 EEPROM_WP SMB_CLK SMB_DATA {18} C69 0.1uF/25V,Y5V C,27} BUF_PCI_RST#SN74CBT3306PWR SOP8_0D65_4D4+V3.3S C253 0.1uF/25V,Y5V C 1 2+V3.3STOPSTAR TECHNOLOGYR522 8.2K R0402 ns51AAndy Han Page Name Size Project Name Custom ICH4-M (PCI/HUB/CPU) P21i Rev AAM24LC02,ATC SO8_50_150ABuffer to reduce loading on PCI_RST#.{7,20,22,26} PCI_RST#SOT23_5 SN74AHC1G08DBV PCI_RST#32of Date: Monday, April 21, 2003 Sheet 17 46 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR2 154354321+V3.3ALR410 10K R0402 PM_RI# R411 10K R0402 PM_SLP_S5# ns R414 10K R0402 PM_BATLOW# R418 10K R0402 PM_CLKRUN# R0K R423 100K R0402+V3.3AL 100K R539 R0402+V3.3SR736 10K R0402 U3B R2 Y3 AB2 T3 AC2 V20 AA1 AB6 Y1 AA6 W18 Y4 Y2 AA2 W19 Y21 AA4 AB3 V1 J21 Y20 V19 R3 V4 V5 W3 V2 W1 W4 Y13 AB14 AB21 AC22 AA13 AB13 W13 AA20 AC20 AC21 AB11 AC11 Y10 AA10 AA7 AB8 Y8 AA8 AB9 Y9 AC9 W9 AB10 W10 W11 Y11 W17 AB17 W16 AC16 W15 AB15 W14 AA14 Y14 AC15 AA15 Y15 AB16 Y16 AA17 Y17 Y12 AB19 AA11 AB18 AC12 Y18 W12 AA18 AB12 AC19 J23 F19 W7 AC7 AC6 Y6 H23 W20 R449 R92 56 R0402 GPIO7 GPIO8 GPIO25 GPIO27 CRB_SET# IDE_PDCS1# IDE_PDCS3# IDE_SDCS1# IDE_SDCS3# IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 {21} {21} {21} {21} {21} {21} {21} {21} {21} {21} R412 10K R413+V3.3S R02 1 1 1 EXTSMI# {26,27} EC_RUNTIME_SCI# {26} EC_WAKE_SCI# {26} TP31 ICTP TP12 ICTP TP13 ICTP+V3.3SDC347 0.1uF/25V,Y5V U36 C} PM_SLP_S1# 4 1 2 3{7} SLP_S1#_D PM_SLP_S3#AGP_BUSY#PM_SYSRST# 1 ICTP{26} PM_BATLOW# TP21 {22,26,27} PM_CLKRUN# {38} PM_DPRSLPVR {26} PM_PWRBTN# {14,26,32} PM_PWROKPM_PWROK PM_RSMRST#SOT23_5 SN74AHC1G08DBVPM_RI# SLP_S1# PM_SLP_S5#+V3.3S1K R0402 AC_SPKR ns R427 10K R0402 AC_SDATAOUT ns R430 1K R0402 PCI_GNTA# PCI_GNTA# ns R432 1K R0402 EEP_DOUT EEP_DOUT nsR425{26} SLP_S1#_D {17} {17} {26} SUS_CLK_EC{26,34} PM_RSMRST# R424 68 R,39} PM_SLP_S3# {26,33,39} PM_SLP_S4# {6,38} PM_STPCPU# {6} PM_STPPCI# SUS_CLK {25,27} PM_SUS_STAT# {3} PM_THRM# {38} PM_GMUXSEL {3} PM_CPUPERF# {7,32} IMVP_PWRGD {29,31} AC_BITCLK {29,31} AC_RST# {29,31} AC_SDATAIN0 {31} AC_SDATAIN1R4480 R0402R428 0 nsR0402ICH4M Straping OptionPM_AGPBUSY#/GPIO6 PM_SYSRST# PM_BATLOW# PM_C3_STAT#/GPIO21 PM_CLKRUN#/GPIO24 PM_DPRSLPVR PM_PWRBTN# PM_PWROK PM_RI# PM_RSMRST# PM_SLP_S1#/GPIO19 ICH4-M PM_SLP_S3# PART B PM_SLP_S4# PM_SLP_S5# PM_STPCPU#/GPIO20 PM_STPPCI#/GPIO18 PM_SUS_CLK PM_SUS_STAT#/LPCPD# PM_THRM# PM_GMUXSEL/GPIO23 PM_CPUPERF#/GPIO22 PM_VGATE/VRMPWRGD AC_BITCLK AC_RST# AC_SDATAIN0 AC_SDATAIN1 AC_SDATAIN2 AC_SDATAOUT AC_SYNC LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ0# LPC_DRQ1# LPC_FRAME# USB_PP0 USB_PP1 USB_PP2 USB_PP3 USB_PP4 USB_PP5 USB_PN0# USB_PN1# USB_PN2# USB_PN3# USB_PN4# USB_PN5# USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_RBIAS USB_RBIAS# GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 ISTGPIO_7 GPIO_8 GPIO_12 GPIO_13 GPIO_25 GPIO_27 GPIO_28 IDE_PDCS1# IDE_PDCS3# IDE_SDCS1# IDE_SDCS3# IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PD}